Graduate Talent (CPU-SoC Silicon Design)

Intel Corporation; Kulim; Hybrid; MYR 90,000 - 120,000; Full time

Job summary

Intel Corporation in Malaysia is seeking a design-focused engineer to train, design and develop the next generation SOC/CPU for Intel products. You will assist in RTL model validation, define design flows and perform physical design tasks.

You will work on integrating third-party IPs, managing signal integrity between power and clock domains, and coordinating with firmware, drivers and OS teams on Android and Windows platforms.

Qualifications

• Bachelor or Master degree in Electronic, Electrical or Computer Engineering.
• Familiarity with VLSI CMOS logic circuit design.
• Proficiency in UNIX and C programming with CAD tools.

Responsibilities

• Involves training, design and development of next generation SOC/CPU for Intel products.
• Assist RTL model validation and develop design flows and physical design tasks.
• Integrate third-party IPs and manage hardware/software interfaces across platforms.

Skills

VLSI CMOS design

UNIX

C programming

CAD tools

Education

Bachelor of Engineering in Electronic, Electrical or Computer Engineering

Master of Science in Electronic, Electrical or Computer Engineering

Tools

CAD tools

Job description

Job Details:

Job Description:

In this position, you will be involving in the training, design and development of next generation SOC/CPU for wide range of Intel products. Your responsibilities will include some of the following but not limited to:

• Assist design unit owner in Register Transfer Level RTL model functional validation. Use CAD tool extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions. Verify the circuit behavior against the original simulation model and first silicon.

• Define VLSI Structural Design methodology and developing design flows. Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration. Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.

• Develop Analog IP on next generation deep submicron process for the Intel’s SOC, perform tasks related to Very-large-scale integration VLSI complementary metal-oxide-semiconductor CMOS IC design, Solid state physics and physical layout. Such tasks may include: Circuit design of high speed clocking related circuits [phase-locked loop PLL, delay-locked loop DLL, bandgap] or high voltage input/output IO [double data rate DDR/LPDDR, General-purpose input/output GPIO, OPIO].

• Responsible for Integration of Third party IPs – Synthesis, functional and/or timing convergence, and pre and post-si debug of IPs developed by various external vendors as well as within the company. Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory LPDDR, storage eMMC, SATA, UFS, peripherals PCIe, USB, and MIPI interfaces in SOC devices. System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android Windows-based tablets and phones.

Qualifications:

You must possess a Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering.

Additional qualifications include:

• Familiarity with Very Large Scale Integration VLSI Complementary Metal-Oxide Semiconductor CMOS logic circuit design

• Well versed in UNIX, C programming and relevant Computer Aided Design CAD tools.

Job Type:

Intel Contract Employee

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Malaysia, Kulim

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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