Senior FPGA IP Design Engineer

mnosys sdn bhd; Bayan Lepas; On-site; MYR 60,000 - 100,000; Full time

Job summary

mnosys sdn bhd is seeking an FPGA HDL/IP design engineer in Penang/Bayan Lepas to contribute to digital design and verification using Verilog, SystemVerilog and VHDL. You will work with various FPGA vendors and simulation tools such as ModelSim or QuestaSim, and collaborate on interfaces like PCIe, Ethernet, USB, DDR and LVDS as well as SPI, I2C and UART.

A Bachelor degree in Electrical/Electronic engineering or equivalent is required, with 1–5 years of FPGA HDL/IP experience.

Qualifications

• Proficiency with HDL design such as Verilog, System Verilog, and VHDL.
• Experience with FPGA development tools for various vendors.
• Experience with simulation tools such as ModelSim and / or QuestaSim.
• Familiar with high-speed interfaces such as PCIe, Ethernet (L1 – L4), USB, DDR, LVDS, etc.
• Familiar with low-speed interfaces such as SPI, I2C, UART, etc.
• Bachelor degree in Electrical/Electronic engineering or equivalent.
• Minimum 1-5 years of direct working experiences in FPGA HDL/IP design experience.
• Fluent in both written and spoken English, ability to work in an international team.
• Good teamwork attitude, collaboration and communication skills.

Education

Bachelor degree in Electrical/Electronic engineering or equivalent

Tools

Verilog

SystemVerilog

VHDL

FPGA development tools

ModelSim

QuestaSim

PCIe

Ethernet (L1–L4)

USB

DDR

LVDS

SPI

I2C

UART

Job description

mnosys sdn bhd is seeking an FPGA HDL/IP design engineer in Penang/Bayan Lepas to contribute to digital design and verification using Verilog, SystemVerilog and VHDL. You will work with various FPGA vendors and simulation tools such as ModelSim or QuestaSim, and collaborate on interfaces like PCIe, Ethernet, USB, DDR and LVDS as well as SPI, I2C and UART.

A Bachelor degree in Electrical/Electronic engineering or equivalent is required, with 1–5 years of FPGA HDL/IP experience.