Entry-Level IC Test Engineer — Semiconductors

Nexperia; Penang; On-site; MYR 78,000 - 100,000; Full time

Job summary

Nexperia in Malaysia, Penang, is seeking an IC test engineer to design and implement cost-effective test strategies for semiconductor devices. You will work on ATE platforms, hardware interfaces, and test software to support analog and mixed-signal IC characterization.

Responsibilities include developing robust ATE test plans, debugging issues, performing parametric tests, and analyzing silicon results to drive yield improvement.

Qualifications

• Bachelor's degree in Electronic Engineering or related field required.
• 0-3 years of semiconductor IC testing on ATE.
• Experience with ATE hardware PCB design.
• Knowledge of test and measurement equipment.

Responsibilities

• Create robust semiconductor IC test strategy for test platform, hardware, software and instrumentation
• Design ATE hardware interface boards and write test programs for IC testing and characterization
• Debug and bring-up ATE test solution to evaluate analog and mixed-signal ICs and perform bench correlation
• Perform parametric tests on ATE with strong defect screening mentality
• Debug device and setup related issues and drive closure independently
• Analyze silicon results, perform statistical analysis, find root causes for yield issues
• Support silicon qualification including qualification hardware development
• Collaborate with cross-functional teams to contribute to device success

Skills

ATE hardware PCB design

Test & measurement equipment knowledge

ATE analog testers experience

Education

Bachelor's degree or above in Electronic Engineering or related field

Tools

Teradyne ETS-88/ETS-364 or other ATE

Job description

Nexperia in Malaysia, Penang, is seeking an IC test engineer to design and implement cost-effective test strategies for semiconductor devices. You will work on ATE platforms, hardware interfaces, and test software to support analog and mixed-signal IC characterization.

Responsibilities include developing robust ATE test plans, debugging issues, performing parametric tests, and analyzing silicon results to drive yield improvement.