Analog Mixed Signal Layout Engineer

UST; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST in Penang, Malaysia seeks an experienced analog and mixed-signal layout engineer to develop full-custom layouts for high-speed I/O and analog IPs. You will optimize layouts for performance, area, and manufacturability, while collaborating with design, verification, and packaging teams to enable successful tape-outs.

The role requires strong CADENCE Virtuoso skills, deep knowledge of DRC/LVS/ERC, and hands-on experience with 7nm or below processes, including Samsung 5nm advantages.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering or a related discipline.
• Strong experience in analog and mixed-signal layout design.
• Hands‑on experience in SerDes I/O, DDR I/O, or other high-speed I/O layouts.
• Experience with PLL and DLL layouts.
• Experience with LDO, Bandgap, and power delivery implementation.
• Experience with pure analog circuit layout.
• I/O floorplanning and power delivery planning.
• I/O ESD layout and analysis.
• C4 bump and RDL implementation.
• Proficient with Cadence Virtuoso Layout Suite and related physical design/layout tools.
• Strong understanding of DRC, LVS, ERC, parasitic effects, and analog layout best practices.
• Experience with advanced process technologies (7nm or below) is required.
• Experience with Samsung 5nm (or below) layout is a strong advantage

Responsibilities

• Develop and implement full-custom layout for analog and mixed-signal circuits.
• Perform layout implementation for SerDes I/O, DDR I/O, and other high-speed I/O interfaces.
• Execute layout for PLL, DLL, LDO, Bandgap, and other analog IPs.
• Design and optimise pure analog circuit layouts with a focus on matching, symmetry, and performance.
• Perform I/O floorplanning and power delivery planning to ensure robust design implementation.
• Develop and verify I/O ESD layouts and support ESD analysis.
• Support C4 bump and Redisribution Layer (RDL) planning and implementation.
• Perform layout verification including DRC, LVS, ERC, and collaborate with design, verification, and package teams to achieve successful tape-out.
• Optimize layouts for performance, area, reliability, and manufacturability using advanced process technologies.

Skills

Analog layout design

Mixed-signal layout

SerDes I/O layout

DDR I/O layout

Power delivery planning

ESD layout

Cadence Virtuoso

DRC/LVS/ERC

Process tech 7nm

Samsung 5nm layout

Education

Bachelor's degree in Electrical/Electronic Engineering

Tools

Cadence Virtuoso Layout Suite

Job description

Key Responsibilities

• Develop and implement full-custom layout for analog and mixed-signal circuits.
• Perform layout implementation for SerDes I/O, DDR I/O, and other high-speed I/O interfaces.
• Execute layout for PLL, DLL, LDO, Bandgap, and other analog IPs.
• Design and optimise pure analog circuit layouts with a focus on matching, symmetry, and performance.
• Perform I/O floorplanning and power delivery planning to ensure robust design implementation.
• Develop and verify I/O ESD layouts and support ESD analysis.
• Support C4 bump and Redistribution Layer (RDL) planning and implementation.
• Perform layout verification including DRC, LVS, ERC, and collaborate with design, verification, and package teams to achieve successful tape-out.
• Optimize layouts for performance, area, reliability, and manufacturability using advanced process technologies.

Requirements

• Bachelor's or Master's degree in Electrical/Electronic Engineering or a related discipline.
• Strong experience in analog and mixed-signal layout design.
• Hands‑on experience in one or more of the following:
• SerDes I/O, DDR I/O, or other high-speed I/O layouts.
• PLL and DLL layouts.
• LDO, Bandgap, and power delivery implementation.
• Pure analog circuit layout.
• I/O floorplanning and power delivery planning.
• I/O ESD layout and analysis.
• C4 bump and RDL implementation.
• Proficient with Cadence Virtuoso Layout Suite and related physical design/layout tools.
• Strong understanding of DRC, LVS, ERC, parasitic effects, and analog layout best practices.
• Experience with advanced process technologies (7nm or below) is required.
• Experience with Samsung 5nm (or below) layout is a strong advantage