Staff Clock & Power Validation Engineer – AI/HPC SoCs

Qualcomm Incorporated

Tijuana

Presencial

MXN 600.000 - 1.200.000

Jornada completa

Hace 8 días
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Descripción de la vacante

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFARI?NA seeks an experienced System Validation Engineer to own end-to-end clock and power validation for premium MSM platforms. You will validate pre-silicon and post-silicon environments, DVFS, PMIC integration, and AI-focused hardware/software interfaces, collaborating across Architecture, Design and Firmware teams.

You will design scalable test plans, develop drivers and tests in C, and automate workflows with Python to ensure robust

Formación

  • Bachelor’s degree in engineering (electronics, computer engineering etc.)
  • 5+ years of relevant experience in SoC validation and/or related areas
  • Proficient in C, Python
  • Experience with lab instruments (multimeter, oscilloscopes, logic analyzers)
  • Exposure to debug tools (JTAG) and ARM-based SoCs
  • Strong problem-solving, analytical and debugging skills

Responsabilidades

  • Own end-to-end bare-metal framework validation for SoC clock and power architectures
  • Develop and validate test plans and strategies with stakeholders
  • Create scalable device drivers and system tests in C
  • Debug complex pre-Si and post-Si issues and provide direction
  • Automate validation workflows using Python and shell
  • Collaborate across teams in different time zones to ensure coverage

Conocimientos

C programming
Python
Debugging
Analytical skills
Team collaboration

Educación

Bachelor's degree in Electronics/Computer Engineering
Master's degree in Electronics/Computer Engineering
PhD in related field

Herramientas

JTAG
Oscilloscope
Logic Analyzer
Multimeter

Descripción del empleo

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFARI?NA seeks an experienced System Validation Engineer to own end-to-end clock and power validation for premium MSM platforms. You will validate pre-silicon and post-silicon environments, DVFS, PMIC integration, and AI-focused hardware/software interfaces, collaborating across Architecture, Design and Firmware teams.

You will design scalable test plans, develop drivers and tests in C, and automate workflows with Python to ensure robust

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