Senior CPU Pre-Si Verification Engineer

Intel Corporation; Región Centro; On-site; MXN 900,000 - 1,200,000; Full time

Job summary

Intel Corporation in Mexico is seeking an experienced CPU Design Verification Engineer to join our on-site team in Guadalajara. You will develop verification plans, run tests, and collaborate with architects and designers to ensure functional and performance targets are met.

The role requires 6+ years in CPU verification, HDL (Verilog/VHDL), UVM or SystemVerilog, Python or Perl scripting, and hands-on simulation.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of experience in CPU design verification or related domains.
• HDL experience: Verilog or VHDL.
• Verification methodologies: UVM, SystemVerilog, or similar.
• Hands-on with simulation tools and debugging techniques.
• Scripting: Python, Perl for automation tasks.
• Must have unrestricted, permanent right to work in Mexico.

Responsibilities

• Develop and implement comprehensive verification plans for CPU designs.
• Execute test cases and analyze results to ensure design functionality and performance.
• Identify, debug, and resolve design issues through simulation and collaboration with design teams.
• Utilize advanced verification methodologies, tools, and techniques to maintain high-quality standards.
• Collaborate with architects, designers, and engineers to meet project objectives within deadlines.
• Document verification processes and results to support continuous improvements.

Skills

Verilog

VHDL

SystemVerilog

UVM

Python

Perl

Debugging

Simulation

Education

Bachelor's in Electrical/Computer Engineering

Master's degree (preferred)

PhD (preferred)

Tools

Questa/SystemVerilog simulators

ModelSim

Job description

Intel Corporation in Mexico is seeking an experienced CPU Design Verification Engineer to join our on-site team in Guadalajara. You will develop verification plans, run tests, and collaborate with architects and designers to ensure functional and performance targets are met.

The role requires 6+ years in CPU verification, HDL (Verilog/VHDL), UVM or SystemVerilog, Python or Perl scripting, and hands-on simulation.