Lead Memory CAD Engineer — Drive HBM & DRAM Innovation

Micron Memory Malaysia Sdn Bhd; Tlaquepaque; Presencial; MXN 900.000 - 1.300.000; Jornada completa

Descripción de la vacante

Micron Technology, Inc. in Guadalajara invites an Sr Engineer, Memory CAD to contribute to advanced memory designs including HBM, DRAM, and emerging technologies.

You will provide day-to-day CAD tool support, collaborate with HBM design, layout, and verification teams, and support mixed-signal, transistor-level IC design processes from layout to tape-out. This requires a strong background in computer or electrical engineering with 5+ years in CAD/design and experience with memory architectures

Formación

• Bachelor’s or preferably a Master’s/PhD in Computer/ Electrical Engineering or CS.
• 5+ years of direct CAD/design experience in mixed-signal IC flows.
• Experience in memory design (DDR3/4/5, LP3/4/5, HBM, NAND) is preferred.

Responsabilidades

• Provide day-to-day CAD tool support and collateral for HBM design teams.
• Collaborate with HBM design, layout and verification teams on capabilities.
• Support mixed-signal, transistor-level IC design from layout to tape-out and verification.

Conocimientos

Memory design experience

IC design collaboration

Agile software sprints

ML for IC design

Educación

Bachelor's or Master/PhD in Computer Engineering / Computer Science / Electrical Engineering

5+ years CAD or Design experience in mixed-signal IC design flows

Herramientas

Place & Route tools

Vendor tool qualification

Software prototypes for IC design

Descripción del empleo

Micron Technology, Inc. in Guadalajara invites an Sr Engineer, Memory CAD to contribute to advanced memory designs including HBM, DRAM, and emerging technologies.

You will provide day-to-day CAD tool support, collaborate with HBM design, layout, and verification teams, and support mixed-signal, transistor-level IC design processes from layout to tape-out. This requires a strong background in computer or electrical engineering with 5+ years in CAD/design and experience with memory architectures