HIG-HBM ENGINEERING MANAGER - LAYOUT

Micron Technology, Inc; Tlaquepaque; Presencial; MXN 900.000 - 1.200.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, and vision plans

Paid family leave

Paid time-off and holidays

Descripción de la vacante

Micron Technology, Inc in Tlaquepaque, Jalisco is seeking an experienced HIG-HBM Engineering Manager to lead a team in designing critical analog, mixed-signal, and digital layouts. The ideal candidate will have over 10 years of experience in layout design within advanced CMOS processes and proven management skills.

This role ensures the quality and on-time delivery of block-level layouts while coordinating with global engineering teams. Benefits include comprehensive medical plans, paid time-off, and an equal opportunity workplace.

Formación

• 10+ years in analog/custom layout design in advanced CMOS process.
• 2+ years managing/layout teams with quality checks.
• Experience with critical block layouts like temperature sensors and PLLs.

Responsabilidades

• Design and develop critical analog and mixed-signal layouts.
• Manage team for layout verification and quality checks.
• Coordinate planning and execution for project schedules.

Conocimientos

Analog/custom layout design

Management

Layout verification (LVS/DRC)

Cadence VLE/VXL

Mentor Graphic Calibre DRC/LVS

Analog layout fundamentals

Educación

BE or MTech in Electronic/VLSI Engineering

Descripción del empleo

Req ID: JR96276 HIG-HBM ENGINEERING MANAGER – LAYOUT

Responsibilities

• Responsible for a team to design and develop critical analog, mixed-signal, custom digital block and full chip level integration support.
• Manage a team to perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on‑time delivery of block‑level layouts with acceptable quality.
• Coordinate and lead planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environments.
• Guide junior and senior team‑members in their execution of sub‑block‑level layouts & review their work.
• Effectively communicate with global engineering teams to assure the success of layout projects.

Minimum Qualifications

• 10+ years’ experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET).
• 2+ years of managing, coordinating or leading layout teams.
• Experience managing or leading layout teams and projects, ensuring quality checks at all stages of layout development.
• BE or MTech in Electronic/VLSI Engineering, or related.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Hands‑on experience creating layout of critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparator, differential amplifier etc.
• Knowledge of analog layout fundamentals (e.g., matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices).
• Understanding of layout effects on the circuit such as speed, capacitance, power and area.
• Ability to understand design constraints and implement high‑quality layouts.
• Multiple tape‑out support experience will be an added advantage.

Benefits

We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.