Atom CPU Layout Design Engineer

Intel Corporation; Región Centro; On-site; MXN 446,000 - 781,000; Full time

Job summary

Intel Corporation seeks a dedicated Atom CPU Layout Design Engineer to drive physical implementation of memory compilers, custom IP blocks, and layout partitions for future generations of Intel Atom processors. The role requires collaboration with circuit and SoC teams to ensure reusable, optimized layouts and robust design automation.

The ideal candidate will have a Bachelor’s in Electrical/Computer Engineering, 6+ months of layout experience, and an advanced level of English, with the position

Qualifications

• 6+ months of experience in layout design.
• Advanced English level.

Responsibilities

• Deliver physical design implementations following layout methodologies.
• Collaborate with circuit design engineers to translate schematics into layouts.
• Contribute across the full design flow from cell to top-level integration.
• Develop or enhance layout scripts and automation to improve productivity.

Skills

Layout design experience

Advanced English

Education

Bachelor's degree in Electrical Engineering or related field

Job description

Job Description

This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position. As an Atom CPU Layout Design Engineer, you will be part of a highly skilled team responsible for the design of future‑generation, high‑performance Intel Atom microprocessors. In this role, you will drive the physical implementation of a variety of memory compilers, custom IP blocks, and layout partitions that directly support Intel’s CPU products. You will work in a dynamic environment where design challenges are complex, assignments are broadly defined, and solutions often require creativity, deep technical knowledge, and strong problem‑solving skills.

Responsibilities

Ensuring all physical design implementations follow best‑in‑class layout methodologies and deliver highly efficient, high‑quality results. Independently performing and driving complex physical design assignments across multiple design stages. Working closely with circuit design engineers to interpret schematics and translate them into optimized physical layouts. Contributing across the full design flow—from leaf‑level cell layout to block‑level and top‑level integration. Partnering with SoC teams and cross‑site design groups to ensure alignment, reuse, and consistency across projects. Developing or enhancing layout scripts, macros, and automation solutions to improve productivity and design robustness (a strong plus).

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field.
• 6+ months of experience in layout design.
• Advanced English level.
• Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred Qualifications

• Master's degree in electronic/Microelectronic Engineering, Computer Engineering, or a related engineering discipline.
• 1+ year of experience or familiarity with Very Large Scale of Integration (VLSI) and Complementary Metal‑Oxide‑Semiconductor (CMOS) logic circuit design.
• 1+ year of knowledge in Unix/Linux operating systems.
• Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type

Experienced Hire

Shift

Shift 1 (Mexico)

Primary Location

Mexico, Guadalajara

Additional Locations

None specified

Inclusion Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on‑site presence.

Additional Information

Job posting details (such as work model, location or time type) are subject to change.

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.

We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel’s official careers website.

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