Remote Staff Layout Engineer – High-Speed SerDes

AMD; Milano; In loco; EUR 65.000 - 95.000; Tempo pieno

Descrizione del lavoro

AMD is seeking an experience analog/mixed-signal layout design engineer to join the SerDes Technology Group in Milano. You will develop high-speed SerDes layouts for CPU/GPU silicon, working with remote teams across time zones.

The role emphasizes collaboration, problem solving, and quality in physical design. You will participate in floor-planning, PDK flows, and post-layout analyses, contributing to the overall layout methodology and productivity improvements.

Competenze

• Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating.
• Strong in high speed signal routing and shielding.
• Experience with LVS/DRC/ERC/ANT/ESD verifications.
• Familiarity with IC manufacturing processes and design flows.
• Experience with high-speed SerDes blocks and PLLs in advanced Fin-FET processes.
• Experience with digital on-top integration flow or digital SOC flow is a plus.

Mansioni

• Layout design of high speed SerDes analog mixed signal circuits per project requirements and specs.
• Block level physical implementation including floor-planning, power distribution, clock and signal routing, analog layout.
• Post-layout circuit performance analysis participation.
• Participation in block/IP/chip level integration activities.
• Estimate schedules and report progress.
• Contribute to layout methodology and flow development.
• Drive layout productivity improvements and automation.
• Supervise layout resources and address quality issues with design teams.

Conoscenze

High speed layout

Analog/mixed-signal layout

Team collaboration

Communication skills

Problem solving

Layout methodology

Formazione

Bachelors or Masters in Computer/ Electrical Engineering

Strumenti

Cadence SKILL

Python

Perl

Tcl

Descrizione del lavoro

AMD is seeking an experience analog/mixed-signal layout design engineer to join the SerDes Technology Group in Milano. You will develop high-speed SerDes layouts for CPU/GPU silicon, working with remote teams across time zones.

The role emphasizes collaboration, problem solving, and quality in physical design. You will participate in floor-planning, PDK flows, and post-layout analyses, contributing to the overall layout methodology and productivity improvements.