Lead Verification Engineer - SystemVerilog/UVM

Infineon Technologies

Bardi

In loco

EUR 90.000 - 120.000

Tempo pieno

11 giorni fa

Ricevi più risposte dai datori di lavoro

Invia un CV specifico per questa offerta in pochi minuti.

Vantaggi offerti da questo lavoro

Competitive salary

Employee benefits

Descrizione del lavoro

Infineon Technologies in Emilia-Romagna, Italy, seeks a Senior Staff Engineer Verification to shape future technologies in our Research & Development team. You will merge creativity with technical expertise in verification for complex mixed-signal designs, driving impactful projects and mentoring engineers.

The role demands leadership, deep SystemVerilog/UVM proficiency, and collaboration across design teams, with a competitive salary and benefits.

Competenze

University degree in Electrical Engineering, Computer Science, IT or similar.
6+ years in Digital Verification; leadership a plus.
Strong skills in SystemVerilog, UVM and verification tools.

Mansioni

Create and define verification plans for digital verification of mixed-signal designs.
Develop and improve verification environments using SystemVerilog, UVM, constrained random methods.
Execute tests on RTL and gate-level; debug design and verification environments.
Lead and coordinate other verification engineers in projects.
Collaborate with analog and digital designers and other verification engineers.
Mentor junior colleagues, consultants and students.
Drive innovations to enhance verification methodologies and flows.