Lead FPGA Architect — Multi-Gigabit Networking

Luxoft; Italia; In loco; EUR 90.000 - 130.000; Tempo pieno

Vantaggi offerti da questo lavoro

Luxoft Training Center

Knowledge sharing meetings

Employee discounts

Friendly environment

Descrizione del lavoro

Luxoft is seeking an experienced Principal FPGA Engineer to own the complete FPGA architecture of next-generation communications test and assurance solutions. You will work on high-performance, multi-gigabit designs and collaborate with global teams from Turin or remote within Italy.

The role requires leadership in architecture decisions, IP selection, and debugging, with hands-on proficiency in Verilog/SystemVerilog/VHDL and high-speed interfaces.

Competenze

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field.
• Excellent experience in FPGA design and architecture.
• Extensive hands-on experience with Verilog, SystemVerilog and/or VHDL.
• Strong expertise in multi-Gbps SerDes, transceivers, PLLs and high-speed Ethernet technologies.

Mansioni

• Define and drive end-to-end FPGA architecture.
• Lead architecture decisions, IP selection, floor-planning strategies and timing closure activities.
• Act as the main technical reference point for FPGA design and debugging activities.
• Mentor engineers and support system integration and board bring-up activities.
• Collaborate closely with global engineering teams.

Conoscenze

FPGA design

Verilog

SystemVerilog

VHDL

SerDes

transceivers

High-speed Ethernet

Optical interfaces

SFP

QSFP

Networking protocols

VLAN

MPLS

VPLS

VoIP

IPTV

AMD/Xilinx

Altera

Formal verification

UVM

Git

Collaboration tools

Formazione

Bachelor's or Master's degree in Electrical/Computer Engineering

Strumenti

Questa

Aldec Riviera

Git

Descrizione del lavoro

Luxoft is seeking an experienced Principal FPGA Engineer to own the complete FPGA architecture of next-generation communications test and assurance solutions. You will work on high-performance, multi-gigabit designs and collaborate with global teams from Turin or remote within Italy.

The role requires leadership in architecture decisions, IP selection, and debugging, with hands-on proficiency in Verilog/SystemVerilog/VHDL and high-speed interfaces.