Design/Senior Design Engineer – NAND Core (NVE Engineering)

1460 Micron Semiconductor Ital; Avezzano; In loco; EUR 34.000 - 57.000; Tempo pieno

Vantaggi offerti da questo lavoro

Meal vouchers

Corporate welfare

Supplementary health insurance

Life coverage

Employee Assistance Program

Descrizione del lavoro

1460 Micron Semiconductor Ital is seeking a Design Engineer to contribute to developing memory products at their Avezzano location. The ideal candidate will have an M.S. or Ph.D. in Electrical Engineering and proven experience in analog and mixed-signal CMOS circuit design.

The role involves designing and optimizing circuit blocks, collaborating across teams, and utilizing automation tools while ensuring power efficiency and manufacturability. A competitive salary package and additional benefits are offered.

Competenze

• Experience in NAND Flash or other non-volatile memory technologies.
• Familiarity with design automation and scripting.
• Understanding of layout constraints in physical design.

Mansioni

• Design, simulate, and optimize NAND core circuit blocks.
• Translate product requirements into circuit implementations.
• Perform comprehensive circuit verification at block and chip level.
• Collaborate with cross-functional teams to improve product performance.
• Develop automation solutions and maintain technical documentation.

Conoscenze

Analog and/or mixed-signal CMOS circuit design

SPICE-based simulation tools

Device physics and reliability

Problem solving

Formazione

M.S. or Ph.D. in Electrical Engineering or related field

Strumenti

Python

Descrizione del lavoro

Position Overview

As a Design Engineer in the NVE Design Engineering Core group at Micron Semiconductor Italia, you will contribute to the development of memory products that are best‑in‑class, using your specialized knowledge and Micron proprietary methods of designing and analyzing core and mixed circuits used in the development of memory products.

Responsibilities

• Design, simulate, and optimize NAND core circuit blocks, balancing performance, power, area, and reliability trade‑offs.
• Translate product and system requirements into circuit implementations, evaluating feasibility and functionality across use cases.
• Perform comprehensive circuit verification (DC, AC, transient, noise, Monte Carlo, PVT corners) at block and chip level.
• Collaborate with cross‑functional teams to improve power efficiency, manufacturability, and overall product performance.
• Develop and leverage automation solutions (e.g., Python‑based workflows, AI‑assisted tools) and maintain technical documentation.

Minimum Qualifications

• M.S. or Ph.D. in Electrical Engineering, Electronics, or a related field.
• Proven experience in analog and/or mixed‑signal CMOS circuit design.
• Solid understanding of device physics, variability, reliability, and power integrity.
• Hands‑on experience with SPICE‑based simulation tools and circuit verification methodologies.
• Strong problem‑solving and communication skills, with ability to work in global cross‑functional teams.

Preferred Qualifications

• Experience in NAND Flash or other non‑volatile memory technologies.
• Familiarity with design automation, scripting (e.g., Python), or AI‑assisted design approaches.
• Understanding of layout constraints and interaction with physical design flows.

Salary & Benefits

Base salary range: 34,000.00€–57,000.00€ per year, with B2 CCNL Level.

Remuneration package also includes eligibility for a variable plan subject to the personal achievement of objectives and the company's performance, and benefits, which at the discretion of the company currently include meal vouchers, corporate welfare, yearly allowance of remote working days, supplementary health insurance, life coverage, Employee Assistance Program.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. Remuneration is determined by objective criteria, regardless of gender and of any other factor protected by applicable federal, state, or local laws.