WiFi MAC Design - Lead Engineer

Qualcomm; Chennai District; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Qualcomm India Private Limited in Chennai recruits a Senior Hardware Engineer to drive high-speed modem hardmacro implementation for 4nm-8nm nodes. You will mentor juniors and collaborate with RTL/DFT/PD teams from Post-RTL to Netlist, shaping area, timing, power and testability.

The role demands strong fundamentals in microarchitecture, circuit design and process tech, plus expertise in synthesis (DC/Genus), formal verification, and UPF power intent to optimize PPA across complex blocks.

Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
• High-speed and Low-power 5G and WLAN Modem Hardmacro Implementation Lead
• Lead, train and mentor team of junior engineers to execute on a complex project for a large modem design in advanced process nodes
• Work closely with RTL, DFT and PD leads worldwide to take a project from Post-RTL to Netlist release, and converge on area, timing, power and testability
• Primary tasks include writing timing constraints, synthesis, formal verification, CLP, Primetime, PTPX, CECO
• Optimize datapath design for low-area, low-power and high-speed using advanced features in synthesis such as MCMM, SAIF, multibit mapping etc.
• Optimize PPA using the right tool options and stdcell libraries / memories
• Handle complex digital blocks with >1M gates in advanced process nodes from 4nm / 5nm / 7nm / 8nm

Responsibilities

• Lead hardmacro implementation for 5G/WLAN modems.
• Mentor junior engineers on complex modem design.
• Collaborate with RTL/DFT/PD teams from Post-RTL to Netlist.
• Write timing constraints and perform synthesis and formal verification.
• Optimize datapath for low-area, low-power, high-speed.

Skills

Microarchitecture

Computer Arithmetic

Circuit Design

Process Technology

Communication skills

Power optimization

Team mentoring

Hardmacro implementation

Education

Bachelor's degree in CS/EE/Engineering

Master's degree in CS/EE/Engineering

PhD in CS/EE/Engineering

Tools

Synthesis (DC/Genus)

Formality/LEC

Conformal Low Power

Primetime

PTPX

CECO

UPF Power Intent

Job description

Job Area

Engineering Group, Engineering Group > Hardware Engineering

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

• Strong fundamentals in core areas: Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology
• Strong communication skills to work with design teams worldwide
• Extensive experience in Synthesis (DC or Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO
• Extensive experience in UPF based power intent and synthesi

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

• High-speed and Low-power 5G and WLAN Modem Hardmacro Implementation Lead
• Lead, train and mentor team of junior engineers to execute on a complex project for a large modem design in advanced process nodes
• Work closely with RTL, DFT and PD leads worldwide to take a project from Post-RTL to Netlist release, and converge on area, timing, power and testability
• Primary tasks include writing timing constraints, synthesis, formal verification, CLP, Primetime, PTPX, CECO
• Optimize datapath design for low-area, low-power and high-speed using advanced features in synthesis such as MCMM, SAIF, multibit mapping etc.
• Optimize PPA using the right tool options and stdcell libraries / memories
• Handle complex digital blocks with >1M gates in advanced process nodes from 4nm / 5nm / 7nm / 8nm

Applicants

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.