Verification Engineer

Luxoft; Hyderabad; On-site; INR 700,000 - 1,100,000; Full time

Job summary

Luxoft in Hyderabad, India, is seeking a Junior FPGA engineer to join a highly regarded team delivering cutting-edge solutions. The role focuses on implementing Xilinx Vivado FPGA flows and ensuring design quality across the FPGA design cycle.

The ideal candidate has 2-4 years of experience, strong debugging skills, and familiarity with timing analysis and constraints, with English at least B2.

Qualifications

• Must have Xilinx Vivado, specifically the implementation flow.
• Knowledge of FPGA design flow and best practices.
• Experience with static timing analysis and design constraints.
• Strong in digital/logic design.
• Good debugging skills and problem-solving mindset.
• 2-4 years of experience in FPGA/EDA roles.
• Nice-to-have: scripting/automation (Tcl, Python) for workflows.

Responsibilities

• Tests the Xilinx Vivado FPGA implementation flow itself.
• Performs placer, routing, and static timing analysis tasks.
• Analyses quality of results; conducts EDA tool QA for FPGA engineering, not ASIC verification.

Skills

Xilinx Vivado

FPGA design flow

Static timing analysis

Digital/logic design

Debug skills

2-4 years experience

Tools

Tcl

Python

Job description

Project description

This is a great opportunity to work as part of a highly regarded team to deliver leading-edge solutions.

Responsibilities

• Tests the Xilinx Vivado FPGA implementation flow itself
• placer, routing, static timing analysis
• and analyses quality of results. EDA tool QA for an FPGA engineer, not ASIC verification.

Skills

Must have

• Xilinx Vivado, specifically the implementation flow
• FPGA design flow
• static timing analysis and design constraints
• digital / logic design
• debug skills
• 2-4 years of experience
• Experience: Minimum 2, maximum 4 years.

Nice to have

• EDA company experience
• scripting / automation (Tcl, Python)
• AI tool usage

Other

Languages: English: B2 Upper Intermediate

Seniority: Junior