Validation Lead

Larsen & Toubro Limited; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LTST-L&T Semiconductor Technologies Limited in Bengaluru seeks a Validation Lead to drive end-to-end validation for semiconductor chip programs. You will lead pre-silicon testability planning, post-silicon functional validation, and cross-functional collaboration with hardware, firmware, and software teams to ensure samples are ready for customer deployment and production.

Qualifications

• End-to-end validation strategy across semiconductor chip programs.
• Involvement in pre-silicon testability planning and post-silicon functional validation.
• Requires 15+ years of experience and leadership in cross-functional teams.

Responsibilities

• Embed testability hooks into chip designs with architecture and design teams.
• Influence board design specs to validate readiness before tape-out.
• Drive validation planning early in the design cycle to minimize downstream risks.
• Lead development of test boards, interfaces, and validation environments.
• Ensure firmware/software integration for validation platforms and execute validation tests.
• Lead defect triage, root-cause analysis, and go/no-go recommendations.

Skills

Leadership

Validation planning

Testability

Hardware

Firmware

Software

Cross-functional collaboration

Education

BE degree

Tools

Test boards

Automation

Debugging tools

Job description

• LTST-L&T Semiconductor Technologies Limited

Posted On 25 Sep 2026

End Date 24 Mar 2027

Required Experience 10 - 20 years

Skills

Knowledge & Posting Location

Validation

Bachelor of Engineering (BE)

Job Description

The Validation Lead is responsible for driving end-to-end validation strategy across semiconductor chip programs at LTSCT, covering both pre-silicon testability planning and post-silicon functional validation. With 15+ years of experience, the role ensures chips meet design specifications by influencing architecture for testability, preparing robust validation environments, executing comprehensive test plans, and leading defect analysis. This position requires a strong blend of hardware, firmware, and software expertise, along with leadership in cross-functional collaboration to ensure chips are ready for engineering samples and customer deployment.

SECTION III: KEY RESPONSIBILITIES/ ACCOUNTABILITIES

• Partner with architecture and design teams to embed testability hooks into chip designs.
• Influence board design specifications to ensure validation of readiness before tape-out.
• Drive validation planning early in the design cycle to minimize downstream risks.

Validation Environment Preparation

• Lead the development of test boards, interfaces, and supporting environments.
• Ensure firmware/software integration for validation platforms.
• Oversee creation of test cases aligned with architectural specifications.
• Direct execution of functional validation across all chip components and features.
• Validate real hardware running firmware/software against design specifications.
• Ensure comprehensive coverage of system-level scenarios and corner cases

Defect Identification & Debugging

• Lead defect triage, documentation, and communication with design teams.
• Drive root cause analysis and corrective validation cycles.
• Provide go/no-go recommendations for engineering sample release.
• Mentor validation engineers and build high-performing teams.
• Define validation methodologies, best practices, and automation strategies.
• Represent validation in cross-functional program reviews and customer engagements.

SECTION IV: KEY INTERACTIONS

Internal Stakeholder

Purpose of Interaction

• Engage during pre-silicon stage on chip architecture, testability requirements, validation planning

Board Design Team

• Define Test board specifications required for validation before chip tape-out.

Software / firmware Team

• Coordinate on firmware and software availability required to run the chip during validation

External Stakeholder

Purpose of Interaction

Customers (Limited)

• support evaluation of engineering samples and provide technical validation insights