Lead Software Engineer

HCLTech; Dadri; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

HCL Technologies Limited is seeking an experienced validation engineer to lead end-to-end SoC validation from pre-silicon readiness through first-silicon power-on and post-silicon sign-off. The role covers validation planning, execution, debug, coverage, and issue closure across hardware, firmware, and software.

You will develop validation plans, run tests on emulation, FPGA/HAPS, and silicon platforms, and drive root-cause analysis with cross-functional teams.

Qualifications

• Relevant experience in end-to-end SoC validation across pre-silicon, bring-up, and post-silicon stages.
• Strong proficiency in C/C++, Python, and test automation.
• Hands-on debugging using JTAG, emulation, FPGA/HAPS, and lab equipment.

Responsibilities

• Develop validation plans, test content, and coverage for IP, subsystem, and SoC features.
• Execute validation on emulation, FPGA/HAPS, and silicon platforms.
• Drive first-silicon power-on, boot-up, bring-up, and feature enablement.
• Perform post-silicon functional, stress, robustness, and system-level validation.
• Debug issues using logs, traces, JTAG, register/memory dumps, and lab tools.
• Drive root-cause analysis and closure with Design, DV, Firmware, Software, and Platform teams.
• Develop / Enable reusable automation, validation frameworks, and regression suites.

Skills

SoC validation

C/C++

Python

JTAG debugging

Automation scripting

Tools

JTAG

FPGA/HAPS

Emulation platforms

Job description

Lead end-to-end SoC validation from pre-silicon readiness through first-silicon power-on and post-silicon sign-off. Own validation planning, execution, debug, coverage, and issue closure across hardware, firmware, and software.

Key Responsibilities

• Develop validation plans, test content, and coverage for IP, subsystem, and SoC features.


• Execute validation on emulation, FPGA/HAPS, and silicon platforms.


• Drive first-silicon power-on, boot-up, bring-up, and feature enablement.


• Perform post-silicon functional, stress, robustness, and system-level validation.


• Debug issues using logs, traces, JTAG, register/memory dumps, and lab tools.


• Drive root-cause analysis and closure with Design, DV, Firmware, Software, and Platform teams.


• Develop / Enable reusable automation, validation frameworks, and regression suites.

Required Skills

• Strong SoC architecture, boot flow, memory, and peripheral knowledge.


• Experience in pre-silicon, bring-up, and post-silicon validation.


• Hands-on debug using JTAG, emulation, FPGA/HAPS, and silicon lab equipment.


• Proficiency in C/C++, Python, scripting, and test automation.


• Strong debug, triage, and root-cause analysis skills.

Preferred

• Experience with DDR/LPDDR, PCIe, USB, Ethernet, Security, and Low-Power validation.


• Exposure to Linux/U-Boot, firmware, BSPs, and device drivers.


• Technical leadership of validation teams and sign-off activities.