Platform Validation Lead / Manager

Kandou AI; Hyderabad; On-site; INR 3,500,000 - 5,000,000; Full time

Job summary

Kandou AI, based in Hyderabad, India, is redefining AI infrastructure economics by reducing the Total Cost of Ownership of hardware systems. We are seeking a Platform Validation Lead/Manager to own the Hyderabad validation strategy and drive pre/post-silicon verification, lab processes and cross-functional collaboration to deliver customer-ready releases.

Ideal candidates will bring 10+ years in silicon or platform validation, strong Python/C++ skills, and proven leadership abilities, with

Qualifications

• 10+ years of silicon, system or platform validation on shipping SoCs.
• Own at least one pre- to post-silicon validation cycle, including bring-up.
• Hands-on system debugging across silicon, boards, firmware and drivers.
• Strong Python automation and C/C++ knowledge.
• Experience with CMIS, I2C/SMBus, SPI, MDIO or MCTP interfaces.
• Proven tech and people leadership; travel ability.

Responsibilities

• Own Hyderabad platform-validation strategy for Ethernet Retimers.
• Lead pre-silicon and post-silicon validation using simulation, FPGA or HIM.
• Validate server and switch host integration and module-management flows.
• Build automated regression, conformance and release-readiness workflows.
• Lead Hyderabad validation team, set up benches and lab processes.
• Collaborate with SoC, DV, firmware, characterization, interoperability teams.

Skills

Python automation

C/C++ knowledge

CI/version control

Lab tools proficiency

System debugging

Education

BS in Electrical Engineering, Computer Engineering or Computer Science

Tools

JTAG

Oscilloscopes

BERTs

CI

Job description

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

We are looking for a Platform Validation Lead/Manager

Location: Hyderabad, India

Responsabilities

• Own the Hyderabad platform-validation strategy for Ethernet Retimers, converting product, silicon, firmware and standards requirements into traceable test plans, entry and exit criteria, sample coverage and release decisions.
• Lead pre-silicon and post-silicon validation using simulation, FPGA or emulation and hardware-in-loop environments; drive first-silicon bring-up through power, clocks, boot, register access and module enumeration.
• Validate server and switch host integration, CMIS module-management state machines, I2C/SMBus and SPI mailbox flows, hot-plug, power sequencing, telemetry, diagnostics and fault recovery.
• Build automated regression, conformance and release-readiness workflows with requirements-to-test traceability, reproducible configurations, a known-failure catalog and evidence-based defect disposition.
• Lead and mentor the Hyderabad validation team; establish benches, equipment and lab processes, plan capacity, review results and remain hands‑on in system‑level debug and root‑cause isolation.
• Partner across Hyderabad, Lausanne and Taiwan with SoC, DV, firmware, characterization, interoperability, product and field teams to correlate results and deliver qualified customer‑ready releases.

Essential Experience

• 10+ years of silicon, system or platform validation experience on shipping SoCs, networking silicon, SerDes, retimers, PHYs, AEC/AOC or optical-module products.
• Direct ownership of at least one pre-silicon-to-post-silicon validation cycle, including first-silicon or board bring‑up, qualification and release‑readiness decisions.
• Hands‑on system debug across silicon, boards, firmware, drivers and host applications, using JTAG, register traces, oscilloscopes, BERTs and related lab tools.
• Strong validation automation skills in Python and working C and/or C++ knowledge; experience with hardware-in-loop frameworks, CI, version control and reproducible test environments.
• Experience validating management and sideband interfaces such as CMIS, I2C//I3CSMBus, SPI, MDIO or MCTP, including state transitions, error paths, hot‑plug and recovery behavior.
• Demonstrated requirements‑traceable validation discipline: verification methods, pass/fail criteria, sample plans, environmental conditions, guard bands and clear evidence packages.
• Proven technical and people leadership, including hiring or mentoring engineers, managing lab priorities and driving cross‑functional defect closure under a fixed schedule.
• Excellent written and verbal communication; BS in Electrical Engineering, Computer Engineering or Computer Science, or equivalent experience. Ability to travel for bring‑up and partner qualification windows.

Useful Experience

• Validation of 100G/lane or 200G/lane Ethernet, PAM4 SerDes, retimers, PHYs, AEC/AOC or optical modules.
• IEEE 802.3, OIF-CEI, CMIS 5.x, OSFP MSA or related electrical and module‑management conformance.
• BER and FEC validation, link training and equalization, loopback test, eye and margin analysis, and correlation with characterization data.
• Secure boot, authenticated firmware update, image signing, rollback and recovery‑path validation.
• Hyperscaler or tier‑one OEM qualification, NIC or switch‑ASIC interoperability, plugfests and customer escalation support.
• ATE or manufacturing‑test correlation, EIA-364 or JEDEC qualification exposure, thermal and power validation, and multi‑site program leadership.