Truechip - DFT Engineer - ATPG & MBIST Implementation

Truechip; Hyderabad; On-site; INR 900,000 - 1,400,000; Full time

Job summary

Truechip is seeking a DFT Engineer to architect and implement Design-for-Test strategies ensuring silicon quality across complex SoCs.

The role involves developing DFT architectures, inserting scans, generating ATPG patterns, and verifying MBIST for embedded memories. You will collaborate with distributed teams and analyze test failures to improve yield and design robustness.

Qualifications

• Experience with industry-standard DFT methodologies, including scan insertion, ATPG and MBIST implementation.
• Proficient in using EDA tools from major vendors to manage end-to-end DFT flow.
• Excellent ability to communicate complex technical challenges to stakeholders.
• Demonstrated adaptability to fast-paced projects across Bangalore, Noida, and Hyderabad.
• Strong analytical mindset with attention to silicon design details.
• 2–15 years hands-on semiconductor experience with Electronics/Electrical Engg background.

Responsibilities

• Develop and implement comprehensive DFT architectures for complex SoCs.
• Generate and validate ATPG patterns for wafer sort and final test.
• Design and verify MBIST architectures for embedded memories.
• Collaborate with cross-functional teams to resolve timing and congestion issues.
• Perform gate-level simulations and timing analyses to ensure robust test modes.
• Support post-silicon debug by analyzing failures and improving yields.

Skills

DFT methodologies

ATPG

MBIST

Stakeholder communication

Distributed team collaboration

Education

Bachelor's degree in Electronics or Electrical Engineering

Master's degree in Electronics or Electrical Engineering

Tools

EDA tools (major vendors)

Job description

Company Overview

Truechip is a leading provider of Verification IP (VIP) solutions, specializing in the development of high-quality, silicon-proven IP for complex SoC designs.

Company Overview

Truechip is a leading provider of Verification IP (VIP) solutions, specializing in the development of high-quality, silicon-proven IP for complex SoC designs.

Operating at the forefront of the semiconductor industry, the company supports global clients in the automotive, mobile, networking, and storage sectors.

Truechip is recognized for its technical depth and commitment to accelerating the time-to-market for next-generation chip architectures through robust verification methodologies and engineering excellence.

Role Overview

As a DFT Engineer at Truechip, you will be responsible for architecting and implementing comprehensive Design-for-Test strategies to ensure the highest levels of silicon quality.

Key Responsibilities

• Develop and execute robust DFT architectures, including scan insertion and test point insertion, to achieve high fault coverage for complex SoC designs.


• Generate and validate ATPG patterns to ensure effective defect detection during wafer sort and final package testing.


• Implement and verify MBIST architectures for embedded memories to ensure reliable memory testing and repair mechanisms.


• Collaborate with cross-functional teams to resolve timing and congestion issues arising from DFT logic insertion.


• Perform gate-level simulations and timing analysis to verify the integrity of test modes and ensure seamless integration with the overall design flow.


• Drive the post-silicon debug process by analyzing test failures and providing actionable insights to improve yield and design robustness.

Required Skillset

• Demonstrated expertise in industry-standard DFT methodologies, including scan insertion, ATPG, and MBIST implementation.


• Strong proficiency in working with EDA tools from major vendors to manage the end-to-end DFT flow.


• Ability to communicate complex technical challenges clearly to stakeholders and collaborate effectively within a distributed engineering team.


• Proven capability to adapt to fast-paced project environments across Bangalore, Noida, and Hyderabad locations.


• Strong analytical mindset with a focus on problem-solving and attention to detail in high-stakes silicon design environments.


• A Bachelors or Masters degree in Electronics or Electrical Engineering, backed by 2 to 15 years of hands‑on experience in the semiconductor domain.

(ref:hirist.tech)