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Microchip Technology Inc. seeks an experienced Design-For-Test Principal Engineer in Bengaluru to deliver advanced DFT architectures and test coverage improvements across multiple business units.
You will lead ATPG/MBIST activities with Tessent/Modus tools, perform on-silicon debug, and collaborate with SoC teams to ensure robust testability and high-quality silicon.
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await!
Microchip AES Design team in Bangalore is looking for an experienced and motivated Design-For-Test Principal Engineer to provide test hardware solution for various microchip Business units. As a member of test development team, you will be responsible for understanding the existing DFT test structures and clock strategy used across multiple business units and provide architectural improvements to improve test coverage. The candidate should have experience with ATPG and MBIST. The candidate should have in depth knowledge of Tessent/Modus tool execution.
Bachelors/Masters in Electronics or equivalent degree with 9+ years of experience
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