Principal Engineer - Design for Test

Microchip Technology Inc.; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Microchip Technology Inc. Bangalore is seeking a Design-For-Test Principal Engineer to deliver test hardware solutions and improve DFT architectures across multiple units.

You will analyze existing DFT structures, refine clock strategy, and work with tools like Tessent/Modus for ATPG, MBIST, and diagnosis, enabling robust test coverage across SoCs.

The role requires 9+ years in electronics, strong communication, and the ability to collaborate across SoC teams.

Qualifications

• Hands-on DFT on hierarchical designs.
• Tessent/Modus ATPG setup and pattern generation.
• Tessent/Modus MBIST hardware generation.
• Tessent/Modus diagnosis tool for on-silicon debug.
• SCAN pattern simulations and debugging.
• ATPG pattern delivery to test engineering.
• Scan Stitching, Scan Compression, MBIST & JTAG.
• Post-silicon DFT bring-up and debug experience.
• SoC-level simulation debug knowledge.
• Excellent written and verbal communication; team player.

Responsibilities

• Provide test hardware solutions and architecture improvements.
• Collaborate with multiple business units to improve test coverage.

Skills

Hierarchical DFT

Tessent ATPG

Tessent MBIST

Tessent diagnosis

Scan patterns

ATPG delivery

Scan Stitching

Scan Compression

MBIST & JTAG

SoC debug

Communication

Team collaboration

Education

Bachelors/Masters in Electronics

Tools

Tessent/Modus ATPG

Tessent/Modus MBIST

Tessent/Modus diagnosis

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description

Microchip AES Design team in Bangalore is looking for an experienced and motivated Design-For-Test Principal Engineer to provide test hardware solution for various microchip Business units. As a member of test development team, you will be responsible for understanding the existing DFT test structures and clock strategy used across multiple business units and provide architectural improvements to improve test coverage. The candidate should have experience with ATPG and MBIST. The candidate should have in depth knowledge of Tessent/Modus tool execution.

Requirements/Qualifications

• Hands on expertise on handling DFT on hierarchical designs.
• Hands on expertise on Tessent/Modus ATPG tool for DFT setup and pattern generations.
• Hands on expertise on Tessent/Modus MBIST tool for MBIST hardware generation.
• Hands on expertise on Tessent/Modus diagnosis tool for on-silicon debug.
• Hands on expertise SCAN pattern simulations and debug.
• ATPG with the pattern delivery to the test engineering team.
• Sound knowledge of Scan Stitching, Scan Compression, MBIST & JTAG Techniques.
• Should have good post silicon DFT bring-up and debug experience.
• Should have a good knowledge of simulation debug and prior experience at SoC level.
• Excellent written and verbal communication skills.
• Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.

Experience

Bachelors/Masters in Electronics or equivalent degree with 9+ years of experience

Travel Time

0% - 25%