Technical Lead I - VLSI

UST; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

UST in Bengaluru is seeking a SoC Verification Engineer to drive verification of complex IPs and full-chip designs. You will develop verification environments, run verification plans, and collaborate with RTL/design teams to ensure high-quality silicon delivery.

The ideal candidate has 5+ years of IP/SoC verification, strong SystemVerilog, UVM, and coverage-driven verification experience, plus familiarity with AMBA, PCIe, Ethernet, and USB protocols.

Qualifications

• 5+ years of IP/SoC verification experience.
• Experience with complete SoC verification lifecycle.
• Strong knowledge of digital design fundamentals and SoC architecture.

Responsibilities

• Develop and execute comprehensive SoC and IP verification plans.
• Build and maintain verification environments using UVM/OVM/VMM.
• Create testbenches with stimuli, monitors, constraints, and checkers.
• Develop directed and constrained-random test scenarios.
• Perform coverage analysis and drive closure.
• Debug failures and perform root-cause analysis.
• Collaborate with RTL/design teams to resolve issues.
• Enhance verification methodologies and reusable components.

Skills

SystemVerilog

Verilog

UVM

AMBA

PCIe

Ethernet

Debugging

Collaboration

Education

Bachelor's or Master's in Electronics/Computer Engineering

Tools

VCS

Xcelium

Questa

Python

Job description

Who we are

We help the world's best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact-touching billions of lives in the process. Visit us at .

Role Description

We help the world's best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact-touching billions of lives in the process. Visit us at .

Summary

UST is looking for a SoC Verification Engineer with strong expertise in SystemVerilog, UVM, and coverage-driven verification for complex IP and SoC designs.

The Opportunity

We are seeking an experienced SoC Verification Engineer to drive the verification of complex digital subsystems and full-chip SoCs. The ideal candidate will be responsible for developing robust verification environments, executing comprehensive verification plans, and collaborating closely with design and architecture teams to ensure high-quality silicon delivery.

Key Responsibilities

• Develop and execute comprehensive SoC and IP verification plans
• Build, maintain, and enhance verification environments using UVM/OVM/VMM methodologies
• Develop testbenches including stimulus generation, monitors, constraints, assertions, scoreboards, and checkers
• Create directed and constrained-random test scenarios to validate functional correctness
• Perform coverage analysis and drive functional and code coverage closure
• Debug simulation failures, perform root-cause analysis, and drive issue resolution
• Collaborate with RTL design and architecture teams to resolve functional issues
• Enhance verification methodologies, automation, and reusable verification components
• Document verification results, review metrics, and provide regular project status updates
• Participate in design reviews and code reviews, providing technical feedback and recommendations

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline
• 5+ years of experience in IP and SoC Verification
• Experience with at least one complete SoC verification project lifecycle
• Strong understanding of digital design fundamentals and SoC architecture
• Strong proficiency in Verilog and SystemVerilog
• Hands-on expertise with UVM/OVM/VMM verification methodologies
• Strong experience in coverage-driven verification methodologies
• Experience verifying complex digital designs and subsystems
• Expertise in industry-standard protocols such as AMBA (AXI/AHB/APB), PCIe, Ethernet, and USB
• Strong debugging, analytical, and problem-solving skills
• Excellent communication and cross-functional collaboration skills

Preferred Qualifications

• Experience with Formal Verification methodologies and tools
• Familiarity with assertion-based verification (SVA)
• Experience in subsystem and full-chip integration verification
• Knowledge of scripting languages such as Python, Perl, Tcl, or Shell
• Experience with simulators such as VCS, Xcelium, or Questa
• Exposure to emulation, FPGA prototyping, or post-silicon validation flows
• Familiarity with regression automation and continuous integration environments

Leadership Expectations

• Take ownership of verification deliverables and sign-off quality
• Drive coverage closure and verification completeness across project milestones
• Proactively identify verification gaps and recommend methodology improvements
• Collaborate effectively with architecture, design, and validation teams
• Mentor junior verification engineers and promote best practices
• Contribute to building scalable, reusable, and efficient verification environments.

What We Believe

We're proud to embrace the same values that have shaped UST since the beginning. Since day one, we've been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone to champion diversity and inclusion and to place people at the centre of everything we do.

Humility

We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

Humanity

Through business, we will better the lives of those less fortunate than ourselves.

Integrity

We honour our commitments and act with responsibility in all our relationships.

Equal Employment Opportunity Statement

UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.

All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.

UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.

• To support and promote the values of UST.
• Comply with all Company policies and procedures

Skills

SoC Architecture, SystemVerilog, UVM, Verilog, Ethernet, Formal Verification, USB, PCIe