TECHNICAL LEAD - FPGA Architectures

Happiest Minds Technologies; Pune District; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Happiest Minds Technologies is seeking an experienced FPGA Technical Lead in Pune to drive pre-silicon validation and ASIC prototyping on Xilinx platforms. The role focuses on RTL migration, partitioning, simulation, synthesis, P&R, and timing closure, with close collaboration across ASIC, Verification, Firmware, and Software teams.

The candidate should have 8-12 years in ASIC prototyping and a strong background in Verilog/SystemVerilog, FPGA flows, and debugging techniques.

Qualifications

• 8-12 years in ASIC Prototyping and Pre-Silicon Validation.
• Strong experience with Xilinx Vivado and FPGA development flows.
• Verilog and SystemVerilog proficiency.
• Experience in FPGA prototyping, timing analysis, and timing closure.

Responsibilities

• RTL migration, partitioning, simulation, synthesis, and place & route.
• Timing closure, FPGA bring-up, and functional validation.
• Debugging with ILA, logic analyzers, oscilloscopes, and protocol analyzers.
• Collaborate with ASIC Design, Verification, Firmware, and Software teams to accelerate SoC/ASIC validation.

Skills

ASIC Prototyping

Xilinx Vivado

Verilog

SystemVerilog

FPGA development flows

Timing analysis

Synthesis

Place & Route

Debugging

Python scripting

Education

BE/BTech/ME/MTech in ECE/EE/CSE

Tools

QuestaSim

ModelSim

Xcelium

VCS

Job description

FPGA Technical Lead

FPGA Technical Lead ? Pre-Silicon Validation

Location: Pune | Experience: 8-12 Years

Seeking an FPGA Technical Lead with expertise in ASIC prototyping and pre-silicon validation on Xilinx FPGA platforms. Responsibilities include RTL migration, partitioning, simulation, synthesis, place & route, timing closure, FPGA bring-up, functional validation, and debugging. Collaborate with ASIC Design, Verification, Firmware, and Software teams to accelerate SoC/ASIC validation.

Required Skills

• 8-12 years in ASIC Prototyping and Pre-Silicon Validation
• Strong experience with Xilinx Vivado and FPGA development flows
• Verilog, SystemVerilog
• FPGA synthesis, implementation, timing analysis, and timing closure
• ASIC/SoC FPGA prototyping experience
• Protocols: SPI, I2C, UART, USB 2.0/3.x, Ethernet, DDR/Memory Interfaces
• Simulation tools: QuestaSim, ModelSim, Xcelium, or VCS
• Debug using ILA, logic analyzers, oscilloscopes, and protocol analyzers
• Preferred: UVM, multi-FPGA systems, ARM SoCs, Python/TCL scripting

Education: BE/BTech/ME/MTech in ECE, EE, CSE, or related field.