TECHNICAL LEAD - FPGA Architectures

Happiest Minds Technologies; Maharashtra; On-site; INR 4,500,000 - 7,000,000; Full time

Job summary

Happiest Minds Technologies in Pune seeks an FPGA Technical Lead with 8-12 years of ASIC prototyping and pre-silicon validation experience on Xilinx FPGA platforms.

You will drive RTL migration, partitioning, simulation, synthesis, place & route, and timing closure, then validate and debug across SoC/ASIC teams to accelerate development.

Required skills include FPGA prototyping, Vivado flows, and strong tool fluency; BE/BTech/ME/MTech in ECE/EE/CSE is expected.

Qualifications

• 8-12 years in ASIC Prototyping and Pre-Silicon Validation.
• Strong experience with Xilinx Vivado and FPGA development flows.
• FPGA synthesis, implementation, timing analysis, and timing closure.
• ASIC/SoC FPGA prototyping experience.
• Protocols: SPI, I2C, UART, USB 2.0/3.x, Ethernet, DDR/Memory Interfaces.
• Simulation tools: QuestaSim, ModelSim, Xcelium, or VCS.
• Debug using ILA, logic analyzers, oscilloscopes, and protocol analyzers.

Responsibilities

• RTL migration, partitioning, simulation, synthesis, place & route, timing closure.
• FPGA bring-up and functional validation; debugging across boards.
• Collaborate with ASIC Design, Verification, Firmware, and Software teams to accelerate SoC/ASIC validation.

Skills

ASIC prototyping

Pre-silicon validation

Xilinx Vivado

FPGA development flows

Timing analysis

Debugging with ILA

UVM

Multi-FPGA systems

ARM SoCs

Python scripting

TCL scripting

Education

BE/BTech/ME/MTech in ECE/EE/CSE

Tools

Vivado

QuestaSim

ModelSim

Xcelium

VCS

Job description

FPGA Technical Lead ? Pre-Silicon Validation
Location: Pune | Experience: 8-12 Years

Seeking an FPGA Technical Lead with expertise in ASIC prototyping and pre-silicon validation on Xilinx FPGA platforms. Responsibilities include RTL migration, partitioning, simulation, synthesis, place & route, timing closure, FPGA bring-up, functional validation, and debugging. Collaborate with ASIC Design, Verification, Firmware, and Software teams to accelerate SoC/ASIC validation.

Required Skills:

• 8-12 years in ASIC Prototyping and Pre-Silicon Validation
• Strong experience with Xilinx Vivado and FPGA development flows
• FPGA synthesis, implementation, timing analysis, and timing closure
• ASIC/SoC FPGA prototyping experience
• Protocols: SPI, I2C, UART, USB 2.0/3.x, Ethernet, DDR/Memory Interfaces
• Simulation tools: QuestaSim, ModelSim, Xcelium, or VCS
• Debug using ILA, logic analyzers, oscilloscopes, and protocol analyzers
• Preferred: UVM, multi-FPGA systems, ARM SoCs, Python/TCL scripting

Education: BE/BTech/ME/MTech in ECE, EE, CSE, or related field.