TECHNICAL LEAD - FPGA Architectures

Happiest Minds Technologies; Pune District; On-site; INR 1,200,000 - 1,800,000; Full time

Benefits offered by this job

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Job summary

Happiest Minds Technologies Pune is seeking an experienced FPGA Technical Lead to drive pre-silicon validation and ASIC prototyping on Xilinx FPGA platforms. You will oversee RTL migration, partitioning, simulation, synthesis, and timing, enabling rapid bring-up and validation of SoC/ASIC designs.

The role requires 8–12 years of hands-on FPGA experience, strong Verilog/SystemVerilog skills, and collaboration with multiple engineering teams to accelerate validation cycles.

Qualifications

• 8–12 years of experience in ASIC prototyping and pre-silicon validation.
• Proficient with Xilinx Vivado and FPGA development flows.
• Strong knowledge of Verilog and SystemVerilog.
• Hands-on FPGA synthesis, place & route, and timing analysis.
• Experience with FPGA-based prototyping for ASIC/SoC projects.
• Familiarity with SPI, I2C, UART, USB 2.0/3.x, Ethernet, and DDR interfaces.
• Experience with simulation tools: QuestaSim, ModelSim, Xcelium, or VCS.
• Ability to debug with ILA, logic analyzers, oscilloscopes, and protocol analyzers.
• Nice-to-have: UVM, multi-FPGA systems, ARM SoCs, Python/TCL scripting.

Responsibilities

• RTL migration, partitioning, and integration for FPGA prototyping.
• Run simulations, perform synthesis and place & route, ensure timing closure.
• FPGA bring-up and functional validation across platforms.
• Collaborate with ASIC Design, Verification, Firmware, and Software teams.
• Accelerate SoC/ASIC validation through cross-team coordination.

Skills

ASIC Prototyping

Pre-Silicon Validation

Xilinx Vivado

FPGA Flows

Verilog/SystemVerilog

Synthesis & Timing

Prototyping SoC/ASIC

SPI/I2C/UART/USB

DDR Interfaces

Simulation Tools

Debug Tools

UVM / ARM SoCs

Education

BE/BTech/ME/MTech in ECE/EE/CSE

Job description

FPGA Technical Lead

FPGA Technical Lead ? Pre-Silicon Validation
Location: Pune | Experience: 8-12 Years

Seeking an FPGA Technical Lead with expertise in ASIC prototyping and pre-silicon validation on Xilinx FPGA platforms. Responsibilities include RTL migration, partitioning, simulation, synthesis, place & route, timing closure, FPGA bring-up, functional validation, and debugging. Collaborate with ASIC Design, Verification, Firmware, and Software teams to accelerate SoC/ASIC validation.

Required Skills:

• 8-12 years in ASIC Prototyping and Pre-Silicon Validation


• Strong experience with Xilinx Vivado and FPGA development flows


• Verilog, SystemVerilog


• FPGA synthesis, implementation, timing analysis, and timing closure


• ASIC/SoC FPGA prototyping experience


• Protocols: SPI, I2C, UART, USB 2.0/3.x, Ethernet, DDR/Memory Interfaces


• Simulation tools: QuestaSim, ModelSim, Xcelium, or VCS


• Debug using ILA, logic analyzers, oscilloscopes, and protocol analyzers


• Preferred: UVM, multi-FPGA systems, ARM SoCs, Python/TCL scripting

Education:

BE/BTech/ME/MTech in ECE, EE, CSE, or related field.