Static Timing Analysis Engineer

intel; Bengaluru; Hybride; INR 4 000 000 - 6 500 000; Plein temps

Résumé du poste

Intel in Bengaluru is seeking a seasoned Physical Design Timing Engineer to advance next-generation SoCs. You will perform timing analysis, generate constraints, and drive timing closure across chip and block levels to deliver peak performance and efficiency.

Collaborating with architecture, clock design, logic, and backend teams, you will define timing models, set PVT conditions, and develop power-aware clocking strategies to align with high-performance and low-power requirements.

Qualifications

• Experience with static timing analysis tools and methodologies.
• Strong timing modeling, verification, constraint generation, and optimization skills.
• Understanding of PVT conditions and their impact on timing analysis.

Responsabilités

• Perform timing analysis and optimize performance at chip and block levels.
• Generate and verify timing constraints to address violations.
• Develop power-optimized clock networks for high-performance, low-power designs.
• Define methodologies for timing models used by the physical design team.
• Set PVT conditions and coordinate with architecture, clock design, and back-end teams.
• Collaborate with cross-functional teams to refine flows and validation.

Connaissances

Static timing analysis

Timing modeling

Cross-functional collaboration

Power-aware clocking

Formation

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Computer Engineering

PhD in Electrical/Computer Engineering

Outils

STA tools

Description du poste

Job Details:

Job Description:

The Role and Impact: As a Physical Design Timing Engineer, you will play a pivotal role in advancing Intel's next-generation SoCs by ensuring their optimal performance and efficiency. Your expertise will directly impact the success of Intel's products, enabling innovation across high-performance computing, AI, and beyond. You will work on cutting-edge designs, collaborating with cross-functional teams to tackle complex challenges while delivering high-quality timing models that empower the physical design team to excel. This is an exciting opportunity to contribute to Intel's mission of shaping the future of technology.

• Perform timing analysis and optimization to ensure design functionality and performance at the chip and block levels.
• Generate and verify timing constraints, addressing and resolving timing violations during SoC development.
• Conduct timing rollups, develop and implement power-optimized clock networks, and ensure alignment with high-performance, low-power guidelines.
• Define and implement methodologies to deliver quality timing models that enhance the efficiency of the physical design process.
• Set process, voltage, and temperature (PVT) conditions for timing analysis based on product plans and operating conditions.
• Collaborate with architecture, clock design, logic design, and backend teams to achieve clocking balance, power delivery optimization, and efficient partitioning.
• Partner closely with the clocking team to refine methodologies and validate integration flows for chip-level timing solutions.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of experience in Physical Design with a Bachelor's degree, 6+ years with a Master's degree, or 4+ years with a PhD.
• Proficiency in static timing analysis tools and methodologies.
• Demonstrated expertise in timing modeling, verification, constraint generation, and optimization techniques.
• Technical understanding of PVT conditions and their application in timing analysis.

Preferred Qualifications:

• Advanced knowledge of SoC development, clocking design principles, and timing methodologies.
• Strong collaboration skills, with a proven ability to work across architecture, logic design, and physical design teams.
• Experience in high-performance computing or low-power design environments.
• Commitment to continuous learning and staying updated on industry advancements.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.