CPU Circuit Design Lead

intel; Bengaluru; Hybrid; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Intel in Bengaluru, India, seeks an experienced engineer to drive memory design analysis for advanced CPUs. Responsibilities include memory block and data path subsystems, timing analysis, and collaboration with layout teams. The role emphasizes high-speed, low-power design, Verilog scripting, and post-silicon memory analysis.

Hybrid work model offered. The position requires a Masters in Electrical/Computer Engineering with 8+ years of experience (or a Bachelors with 10+ years), and strong

Qualifications

• Masters Degree in Electrical or Computer Engineering with at least 8 years of experience, or a Bachelors Degree with at least 10 years of experience.
• Preferred qualifications include Digital Design experience with high speed and low power, familiarity with Verilog, Tcl/Perl/Python scripting, good understanding of spice simulations and analysis, and strong verbal and written communication skills.

Responsibilities

• Lead design analysis and methodologies for memory blocks and data path subsystems.
• Enable memory block methodologies to meet over 5GHz frequency and low-power digital designs with optimal area.
• Deep understanding of SRAM/RF/ROM memory concepts.
• Expertise in static timing analysis concepts.
• Collaborate with Layout and Floorplanning teams.
• Back-end design implementation of new features.
• Memory post-silicon analysis expertise.
• Understand statistical variation.

Skills

Memory design

Static timing analysis

Verilog

Scripting (Tcl/Perl/Python)

Low-power design

Digital design

Education

Masters in Electrical/Computer Engineering

Bachelors in Electrical/Computer Engineering

Tools

Synthesis tools

P&R tools

Job description

Job Details:

Job Description:

You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems. Your responsibilities will include but not limited to:

• Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.
• In depth understanding of different memory design concepts ((SRAM/RF/ROM).
• Expertise in Static timing analysis concepts.
• Close work with Layout and Floor planning teams.
• Back-end design implementation of new features.
• Expertise in Memory post silicon analysis.
• Good understanding of statistical variation.

Qualifications:

You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred.

Preferred Qualifications:

• Digital Design Experience, with High Speed, Low Power.
• Familiarity with Verilog.
• Tcl, Perl, Python scripting.
• Good understanding of spice simulations and analysis
• Strong verbal and written communication skills.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.