CPU Circuit Design Lead

Intel Corporation; Mumbai; Hybrid; INR 2,800,000 - 3,600,000; Full time

Job summary

Intel Corporation in India (ACE India, P-Core design team) seeks an experienced memory design engineer to lead design analysis for memory blocks and data path subsystems. The role targets >5GHz timing with low power and area efficiency, requiring strong Verilog and scripting skills and deep memory concepts.

The candidate will collaborate with Layout/Floorplanning, perform back-end feature integration, and conduct memory post-silicon analysis in a hybrid work model at India, Bangalore.

Qualifications

• Masters in Electrical or Computer Engineering with 8+ years (or Bachelor's with 10+ years) of related experience.
• Expertise in memory design concepts (SRAM/RF/ROM) and timing analysis.
• Proficiency with Verilog and scripting (Tcl, Python, Perl).

Responsibilities

• Lead design analysis and methodologies for memory blocks and data path subsystems.
• Enable methodologies to meet >5GHz frequency and low power with optimal area.
• Understand SRAM, ROM, and RF memory concepts.
• Apply static timing analysis to ensure timing closure.
• Collaborate with Layout and Floorplanning teams.
• Back-end design implementation of new features.
• Memory post-silicon analysis.

Skills

Memory design

Static timing analysis

Verilog

Tcl scripting

Python scripting

Perl scripting

Education

Master's in Electrical or Computer Engineering

Bachelor's in Electrical/Computer Engineering

Tools

Synthesis tools

Place & Route tools

SPICE simulation

Job description

Job Details: Job Description: You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.

In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems. Your responsibilities will include but not limited to:

• Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.
• In depth understanding of different memory design concepts (SRAM/RF/ROM).
• Expertise in Static timing analysis concepts.
• Close work with Layout and Floor planning teams.
• Back-end design implementation of new features.
• Expertise in Memory post silicon analysis.
• Good understanding of statistical variation.

Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred.

Preferred Qualifications

• Digital Design Experience, with High Speed, Low Power.
• Familiarity with Verilog.
• Tcl, Perl, Python scripting.
• Good understanding of spice simulations and analysis
• Strong verbal and written communication skills.

Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change. Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.