Staff / Principal Engineer- India

Vayavya Labs Pvt. Ltd; India; Sur place; INR 2 500 000 - 4 500 000; Plein temps

Résumé du poste

Vayavya Labs Pvt. Ltd. is seeking a Staff/Principal Engineer to architect and lead the vehicle compute and networking stack, bridging autonomy software with hardware platforms.

You will own the technical roadmap for hardware health monitoring, ensure scalable interfaces, and drive architectural decisions across software, hardware, and systems teams. In this hands-on leadership role, you will code and mentor while tackling Linux kernel tuning, multi-layer networking, and diagnostics for ECUs,

Qualifications

• 7+ years of software engineering, including leading large-scale architecture at the hardware/software interface.
• Expert-level C++ for high-performance, thread-safe Linux systems.
• 5+ years of system-level development: Linux networking stacks, performance profiling, and hardware bring-up.
• Deep command of networking protocols across the stack - low-level CAN/UDP/TCP and high-level gRPC/RTP/HTTP.
• Demonstrated cross-functional leadership across software, hardware, and systems teams, with a track record of shipping complex platforms.

Responsabilités

• Architect and lead the design of the vehicle compute and networking stack, ensuring a modular, scalable interface between autonomy software and hardware platforms.
• Drive the technical roadmap for hardware health monitoring and fleet-wide performance optimization.
• Lead cross-functional integration of new sensors and embedded devices, and define standards for low-latency data interfaces.
• Establish engineering standards for Hardware-in-the-Loop (HIL) testing and automated performance profiling.
• Provide technical oversight on complex system-level issues spanning Linux kernel tuning, high-performance C++, and multi-layer networking (OSI Layers 1-4).
• Define the architecture for on-target diagnostics and self-test - CPU, communication, and memory load generation, power-on self-tests, controlled shutdown/sleep sequences, voltage-fault detection with safe-state entry, and memory/logic BIST - and set standards for how these are triggered, monitored, and reported across ECUs.
• Establish standards for communication bus health and error monitoring across CAN and Ethernet, including link integrity, cable faults, and signal-integrity detection, with fleet-level logging and reporting.
• Mentor senior engineers and raise the technical bar for design, code quality, and system reliability across teams.

Connaissances

C++ high-performance

Linux kernel tuning

CAN/UDP/TCP networking

Cross-functional leadership

System-level development

Outils

C++ toolchain

HIL testing tools

Networking simulators

Description du poste

Experience: 7+ Years

Vayavya Labs builds embedded software and firmware for the semiconductor and automotive industries, with deep expertise in low-level device software, driver automation, and safety-critical systems. Our engineers work close to the metal - from silicon bring-up to production firmware - and increasingly at the compute and networking layer that connects autonomy software to the vehicle’s hardware platforms. This is a role for a technical leader who wants to shape that stack end-to-end.

About the Role

We are looking for a Staff/Principal Engineer to architect and lead the design of the vehicle compute and networking stack - the modular, scalable interface between autonomy software and the underlying hardware platforms. You will own the technical roadmap for hardware health monitoring and fleet-wide performance optimization, set the engineering standards that keep our platforms fast and dependable, and provide deep technical oversight across software, hardware, and systems teams.

This is a hands-on leadership position. You will still be in the code and on the bench for the hardest problems - from Linux kernel tuning to multi-layer networking - while mentoring senior engineers and driving architectural decisions that scale across the fleet.

What You’ll Do

• Architect and lead the design of the vehicle compute and networking stack, ensuring a modular, scalable interface between autonomy software and hardware platforms.
• Drive the technical roadmap for hardware health monitoring and fleet-wide performance optimization.
• Lead cross-functional integration of new sensors and embedded devices, and define standards for low-latency data interfaces.
• Establish engineering standards for Hardware-in-the-Loop (HIL) testing and automated performance profiling.
• Provide technical oversight on complex system-level issues spanning Linux kernel tuning, high-performance C++, and multi-layer networking (OSI Layers 1-4).
• Define the architecture for on-target diagnostics and self-test - CPU, communication, and memory load generation, power-on self-tests, controlled shutdown/sleep sequences, voltage-fault detection with safe-state entry, and memory/logic BIST - and set standards for how these are triggered, monitored, and reported across ECUs.
• Establish standards for communication bus health and error monitoring across CAN and Ethernet, including link integrity, cable faults, and signal-integrity detection, with fleet-level logging and reporting.
• Mentor senior engineers and raise the technical bar for design, code quality, and system reliability across teams.

What You’ll Bring

• 7+ years of software engineering experience, including leading large-scale architecture at the hardware/software interface.
• Expert-level C++ for high-performance, thread-safe, memory-efficient Linux systems.
• 5+ years of system-level development: Linux networking stacks, performance profiling, and hardware bring-up.
• Deep command of networking protocols across the stack - low-level (CAN, UDP, TCP) and high-level (gRPC, RTP, HTTP).
• Demonstrated cross-functional leadership across software, hardware, and systems teams, with a track record of shipping complex platforms.
• Strong systems-debugging instincts - the ability to reason across the boundary from application code down to kernel, driver, and hardware behavior.

Nice to Have

• Experience with autonomy sensors - lidar, radar, and camera - and their integration into low-latency data pipelines.
• Time-Sensitive Networking protocols (PTP / gPTP) and Ethernet switching.
• Functional safety frameworks such as ISO 26262.
• Heterogeneous compute performance optimization across CPU, GPU, and accelerators.
• Networking certifications.
• Experience building distributed fleet health-monitoring frameworks.

Why Join Us

You’ll set the technical direction for the compute and networking backbone of autonomous-vehicle platforms - work that spans silicon to fleet, and code to architecture. It’s a role for an engineer who wants both the ownership of a principal-level mandate and the satisfaction of solving the deepest system-level problems on real hardware.