Staff Physical Design Engineer-DPG-LPDDR

micron; Hyderabad; On-site; INR 3,500,000 - 9,000,000; Full time

Job summary

Micron is seeking a senior Physical Design lead to own RTL-to-GDSII for complex SoCs, guiding floor planning, CTS, P&R, timing closure, and signoff across advanced technology nodes. The role requires hands-on expertise with major EDA tools and a proven tape-out record.

You will mentor global teams, drive AI-enabled design improvements, and collaborate with Architecture, RTL, DFT, Verification, CAD, and Product Engineering to resolve challenging implementation issues.

Qualifications

• 15+ years of hands-on Physical Design experience with multiple SoC tape-outs.

Responsibilities

• Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes.
• Drive floor planning, power planning, CTS, place & route, timing closure, and physical signoff.
• Own PPA optimization, low-power implementation, congestion management, and design convergence.
• Lead STA, SI, EM/IR, DRC, LVS, and reliability closure to achieve tape out readiness.
• Define physical design methodologies, automation strategies, and flow improvements.
• Partner with Architecture, RTL, DFT, Verification, CAD, and Product Engineering teams to resolve complex implementation challenges.
• Provide technical leadership, mentor engineers, and drive execution across global teams.
• Hands-on custom layout design experience is a strong value-added skill, enabling analog/mixed-signal integration, layout optimization, and advanced-node design challenges
• Leverage AI tools to improve RTL-to-GDSII design productivity, quality, and turnaround time.
• Drive adoption of Generative AI and Agentic AI solutions for physical design automation, design closure, and engineering workflow optimization.

Skills

RTL to GDSII

Floor planning

PPA optimization

Low-power design

Custom layout

Python scripting

AI in EDA

Leadership

Signoff tools

Education

B. Tech / M. Tech in Electrical Engineering, VLSI, or related field

Tools

ICC2/Fusion Compiler

Innovus

PrimeTime

Calibre

EM/IR analysis

Job description

Key Responsibilities

• Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes.
• Drive floor planning, power planning, CTS, place & route, timing closure, and physical signoff.
• Own PPA optimization, low-power implementation, congestion management, and design convergence.
• Lead STA, SI, EM/IR, DRC, LVS, and reliability closure to achieve tape out readiness.
• Define physical design methodologies, automation strategies, and flow improvements.
• Partner with Architecture, RTL, DFT, Verification, CAD, and Product Engineering teams to resolve complex implementation challenges.
• Provide technical leadership, mentor engineers, and drive execution across global teams.
• Hands-on custom layout design experience is a strong value-added skill, enabling analog/mixed-signal integration, layout optimization, and advanced-node design challenges
• Leverage Artificial Intelligence (AI) tools to improve RTL-to-GDSII design productivity, quality, and turnaround time.
• Drive adoption of Generative AI and Agentic AI solutions for physical design automation, design closure, and engineering workflow optimization.

Qualifications

• B. Tech/M. Tech in Electrical Engineering, VLSI, or related field.
• 15+ years of hands-on Physical Design experience with multiple successful SoC tape outs.
• Strong expertise in Floor planning, CTS, P&R, STA, Low-Power Design, Physical Verification, and Signoff.
• Hands-on experience with ICC2/Fusion Compiler, Innovus, PrimeTime, Calibre, and EM/IR analysis tools.
• Proficiency in Tcl, Python, Perl, or Shell scripting.
• Strong technical leadership, problem-solving, and stakeholder management skills.
• Proven track record of leading large-scale SoC RTL-to-GDSII programs, defining implementation strategy, and delivering first-pass silicon success.
• Experience in AI/ML, HPC, CPU, GPU, Networking, or Memory SoC designs.
• Demonstrated success driving physical design methodology, automation, and organizational technical excellence.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.