Digital Design Engineer, DMTS/SMTS/MTS

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 3,600,000 - 5,200,000; Full time

Job summary

Micron Technology, Inc. in Hyderabad seeks a senior ASIC frontend engineer to design, develop, and deliver high-quality RTL for complex memory blocks, guiding projects from architecture through implementation while meeting performance, power, and area targets.

You will own RTL, linting, CDC/RDC verification, timing closure, and design constraints, collaborating with architecture, verification, circuit, and physical teams to ensure robust silicon and timely delivery.

Qualifications

• Advanced proficiency in RTL design and microarchitecture using Verilog and SystemVerilog.
• Experience taking designs from architecture to RTL, verification, synthesis and timing closure.
• 10+ years of ASIC or SoC front-end design experience; leadership for senior roles.

Responsibilities

• Design, develop, and deliver high-quality RTL for complex DRAM, memory, and mixed-signal blocks.
• Own front-end ASIC design activities including RTL, linting, CDC/RDC verification, and timing closure.
• Develop and optimize design constraints (SDC, clock, I/O, UPF power intent).
• Collaborate with architecture, verification, circuit, and physical teams to resolve integration challenges.
• Analyze synthesis and timing reports to drive improvements and meet targets.
• Contribute to design methodologies, automation, and RTL-to-GDS flows.

Skills

RTL design

Verilog

SystemVerilog

Synthesis

Timing closure

Front-end ASIC

Automation

Collaboration

Education

Bachelor's degree in EE/CE

Master's preferred

Tools

EDA tools

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Key Responsibilities

• Design, develop, and deliver high-quality RTL for complex DRAM, memory, and mixed-signal digital blocks, driving projects from architecture and specification through implementation handoff while meeting performance, power, area, and quality targets.
• Own front-end ASIC design activities, including RTL development, linting, CDC/RDC verification, functional validation, logic synthesis, static timing analysis (STA), timing constraint definition, and timing closure across multi-mode, multi-corner operating conditions.
• Develop, maintain, and optimize design constraints (SDC), including clock definitions, timing exceptions, I/O constraints, UPF-based power intent, and low-power implementation methodologies to achieve optimal PPA.
• Collaborate closely with architecture, verification, circuit design, and physical implementation teams to resolve integration challenges, improve design robustness, and ensure successful product execution.
• Analyze synthesis and timing reports, identify critical bottlenecks, and drive design improvements to meet performance, power, area, and schedule objectives.
• Chip in to the development and enhancement of design methodologies, automation frameworks, and RTL-to-GDS implementation flows, improving engineering productivity, design quality, and time-to-market.
• Apply strong expertise in CMOS digital and mixed-signal concepts, Verilog/System Verilog, and industry-standard EDA tools to develop scalable and reliable silicon solutions.
• Champion continuous improvement initiatives by demonstrating automation, AI-assisted engineering technologies, and generative AI tools to enhance design efficiency, collaboration, and overall engineering effectiveness.
• Demonstrate strong problem-solving, communication, and collaboration skills while mentoring peers and chipping in to a culture of technical excellence and innovation.

Qualifications

• Bachelor’s or Master’s degree or equivalent experience in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 10+ years of relevant ASIC or SoC design experience, with significant ownership of complex front-end design projects.
• For a principal or senior technical-lead position, 12–15+ years may be preferred.
• Advanced proficiency in RTL design and microarchitecture development using Verilog and SystemVerilog.
• Validated ability to take designs from architecture and specification through RTL implementation, verification support, synthesis, timing closure, and implementation handoff.

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.