Staff Physical Design Engineer-DPG-LPDDR

Micron Technology, Inc; Hyderabad; On-site; INR 3,500,000 - 6,000,000; Full time

Benefits offered by this job

Medical/Dental/Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in Hyderabad, India, seeks a Semiconductor Design Engineer 4 to lead end-to-end RTL-to-GDSII for complex SoCs on advanced nodes. You will drive floor planning, CTS, P&R, timing closure, and signoff, while owning PPA optimization and low-power design.

You will mentor engineers and collaborate with Architecture, RTL, DFT, Verification, CAD, and Product teams to resolve challenges. You should have 15+ years of hands-on Physical Design experience with multiple tape-outs and a

Qualifications

• B. Tech/M. Tech in Electrical Engineering, VLSI, or related field.
• 15+ years of hands-on Physical Design experience with multiple successful SoC tape outs.
• Strong expertise in Floor planning, CTS, P&R, STA, Low-Power Design, Physical Verification, and Signoff.
• Hands-on experience with ICC2/Fusion Compiler, Innovus, PrimeTime, Calibre, and EM/IR analysis tools.
• Proficiency in Tcl, Python, Perl, or Shell scripting.
• Strong technical leadership, problem-solving, and stakeholder management skills.
• Proven track record of leading large-scale SoC RTL-to-GDSII programs, defining implementation strategy, and delivering first-pass silicon success.

Responsibilities

• Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes.
• Drive floor planning, power planning, CTS, place & route, timing closure, and physical signoff.
• Own PPA optimization, low-power implementation, congestion management, and design convergence.
• Lead STA, SI, EM/IR, DRC, LVS, and reliability closure to achieve tape out readiness.
• Define physical design methodologies, automation strategies, and flow improvements.
• Partner with Architecture, RTL, DFT, Verification, CAD, and Product Engineering teams to resolve complex implementation challenges.
• Provide technical leadership, mentor engineers, and drive execution across global teams.
• Hands-on custom layout design experience is a strong value-added skill, enabling analog/mixed-signal integration, layout optimization, and advanced-node design challenges
• Leverage Artificial Intelligence (AI) tools to improve RTL-to-GDSII design productivity, quality, and turnaround time.
• Drive adoption of Generative AI and Agentic AI solutions for physical design automation, design closure, and engineering workflow optimization.

Skills

Floor planning

Place & Route

STA

Low-Power Design

Physical Verification

Signoff

Tcl

Python

Shell scripting

Education

B.Tech/M.Tech in Electrical Engineering, VLSI or related field

Tools

ICC2/Fusion Compiler

Innovus

PrimeTime

Calibre

EM/IR analysis tools

Job description

Key Responsibilities

• Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes.
• Drive floor planning, power planning, CTS, place & route, timing closure, and physical signoff.
• Own PPA optimization, low-power implementation, congestion management, and design convergence.
• Lead STA, SI, EM/IR, DRC, LVS, and reliability closure to achieve tape out readiness.
• Define physical design methodologies, automation strategies, and flow improvements.
• Partner with Architecture, RTL, DFT, Verification, CAD, and Product Engineering teams to resolve complex implementation challenges.
• Provide technical leadership, mentor engineers, and drive execution across global teams.
• Hands-on custom layout design experience is a strong value-added skill, enabling analog/mixed-signal integration, layout optimization, and advanced-node design challenges
• Leverage Artificial Intelligence (AI) tools to improve RTL-to-GDSII design productivity, quality, and turnaround time.
• Drive adoption of Generative AI and Agentic AI solutions for physical design automation, design closure, and engineering workflow optimization.

Qualifications

• B. Tech/M. Tech in Electrical Engineering, VLSI, or related field.
• 15+ years of hands-on Physical Design experience with multiple successful SoC tape outs.
• Strong expertise in Floor planning, CTS, P&R, STA, Low-Power Design, Physical Verification, and Signoff.
• Hands-on experience with ICC2/Fusion Compiler, Innovus, PrimeTime, Calibre, and EM/IR analysis tools.
• Proficiency in Tcl, Python, Perl, or Shell scripting.
• Strong technical leadership, problem-solving, and stakeholder management skills.
• Proven track record of leading large-scale SoC RTL-to-GDSII programs, defining implementation strategy, and delivering first-pass silicon success.
• Experience in AI/ML, HPC, CPU, GPU, Networking, or Memory SoC designs.
• Demonstrated success driving physical design methodology, automation, and organizational technical excellence.

Job Profile(s):

Semiconductor Design Engineer 4

Relocation level: (TBD)

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.