Staff Engineer - Verification

Infineon Technologies AG; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

An established industry player in semiconductor solutions is seeking a skilled verification engineer to join their innovative team. In this role, you will leverage cutting-edge verification tools and methodologies to ensure the functional verification of complex memory devices. With a focus on developing test benches using System Verilog and UVM, your expertise will be crucial in driving decarbonization and digitalization solutions. This opportunity offers a dynamic environment where your contributions will lead to impactful advancements in green energy and smart IoT. If you're ready to take on this challenge, we encourage you to apply and be part of a mission-driven organization.

Qualifications

• 7+ years of experience in constrained-random verification environments.
• Expertise in developing test benches from scratch using SystemVerilog and UVM.

Responsibilities

• Designing self-checking test benches using modern verification techniques.
• Analyzing and debugging simulation failures to ensure zero defect outcomes.

Skills

System Verilog

UVM

C coding

Debugging skills

Functional simulations

Education

Engineering degree in Electrical/Electronic

Tools

Gate Level simulations

Formal verification methods

Job description

In your new role you will:

1. Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices.
2. Responsible for:
   • Designing self-checking test benches using modern verification techniques
   • Implementing functional coverage and assertions using System Verilog and UVM
   • Developing testbench environment using SV and UVM
   • Developing test and functional coverage plans based on device specifications
   • Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes

Your Profile

You are best equipped for this task if you have:

• An engineering degree in Electrical/Electronic streams or equivalent experience
• 7+ years of experience in constrained-random, coverage-driven verification environments
• Experience in developing test benches from scratch using SystemVerilog (SV), HDL, and UVM (Universal Verification Methodology)
• Expertise in Gate Level simulations (GLS) and debugging, root causing real netlist issues
• A solid understanding of verification concepts and experience designing class-based test benches
• C coding, Formal verification methods, and Power-aware simulation experience (advantage)
• Excellent written and oral communication skills
• Strong debugging skills, functional simulations, and GLS simulations

Contact:

Gowri Shenoy, LinkedIn

Our Mission

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions for power systems and IoT, Infineon enables innovative solutions for green energy, clean mobility, and smart IoT. Join us in making life easier, safer, and greener.

Our Commitment

We embrace diversity and inclusion, offering a respectful and equal opportunity environment. We select candidates based on experience and skills. Please inform your recruiter if you need any specific considerations during the hiring process.