Principal Engineer Verification

Infineon Technologies AG; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Infineon Technologies AG in Hyderabad seeks a senior ASIC verification engineer to perform and supervise detailed simulation, verification and validation of integrated circuits.

You will develop testbenches using SystemVerilog and UVM for functional and power-aware RTL, and drive closure of verification metrics. Collaboration with cross-functional teams, post-silicon bring-up, and compliance testing are part of the role.

Qualifications

• Proven expertise in UVM and SystemVerilog based verification.
• Strong understanding of ASIC verification methodologies.
• Experience with source control, bug tracking and release tools such as Git, Jira and Jenkins.

Responsibilities

• Perform and supervise detailed simulation, verification and validation of ICs.
• Develop testbenches using SystemVerilog and UVM for functional and power-aware RTL.
• Develop UVM components like agents, scoreboards and environments; create assertions and coverage.
• Drive closure of verification metrics to cover the verification space.
• Review industry standards and augment test plans to improve quality; participate in design reviews.
• Collaborate with cross-functional teams and assist in post-silicon bring-up and compliance testing.

Skills

UVM

SystemVerilog

Regression testing

Communication skills

Education

Bachelor's in Electrical Engineering

Tools

Git

Jira

Jenkins

Job description

Perform and supervise detailed Simulation, verification and validation of integrated circuits. Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM components like agents (active and passive), scoreboards and environments etc., develop assertions, functional coverage. Develop test plans, UVM based test sequences, layered sequences, virtual sequencers Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware, and gate level timing simulation. Provide regression setup, debug of RTL and gate level netlist. Review industry standard spec and augment test plan to improve quality of verification Participate in post silicon bring up, validation and compliance testing and debug Work collaboratively with cross-functional teams like Product Architect, Designers, Project leads, Project managers Subject matter expert level communication with customer (and/or marketing), including presentation in design reviews, representing the verification team on weekly conference calls, defining/tracking/working to ensure schedule adherence, interactive problem solving, and customer communication under pressure, etc. Bachelor's in electrical engineering or equivalent and 12+ years of experience Proven expertise with UVM and/or System Verilog based verification Excellent understanding of ASIC verification methodologies and proven experience of verification Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira. Strong written and verbal communication skills and ability to work independently.

We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.