Staff Engineer – Synthesized Model IP Design

Nutanix; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Qualcomm India Private Limited seeks a Staff Engineer with 10+ years in ASIC/SoC design to develop synthesized IP models for emulation and FPGA prototyping. You will lead RTL design, C/C++ modeling, and drive integration across design and verification teams.

The role emphasizes architecture contributions, project planning, and mentoring junior engineers, with hands-on FPGA flows and timing closure responsibilities in a collaborative environment.

Qualifications

• Bachelor's or higher in Electrical/Electronics/CS with 4+ years hardware engineering or equivalent.
• 10+ years in ASIC/SoC/FPGA/emulation/prototyping domains.
• Experience delivering complex IP or SoC projects from development through validation.

Responsibilities

• Lead design of synthesizable IP models for emulation and FPGA prototyping.
• Contribute to architecture, micro-architecture discussions and design reviews.
• Develop RTL in Verilog/SystemVerilog with focus on timing, area, and performance.
• Create C/C++ reference models aligned with RTL implementations.
• Drive IP integration, debug, and bring-up across sim, emulation, and FPGA ecosystems.
• Support FPGA synthesis, timing closure, hardware validation, and performance tuning.
• Collaborate with architecture, verification, software, and platform teams for bring-up.
• Prepare project plans, estimate schedules, identify risks, and drive milestones.
• Mentor 2-4 engineers and promote engineering best practices.
• Promote automation and AI-assisted design methodologies.

Skills

RTL design

C/C++ modeling

Verilog/SystemVerilog

IP modeling

Digital design

System-level integration

Education

Bachelor's degree in Electrical, Electronics, or Computer Engineering

Master's degree in Electrical/CS Engineering

PhD in related field

Tools

Xilinx FPGA

Vivado

Siemens Veloce

Cadence Zebu

Git CI/CD

Job description

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary: We are seeking a Staff Engineer with 10+ years of experience in ASIC/SoC design to develop and deliver synthesized IP models for emulation and FPGA prototyping platforms. The ideal candidate will possess strong expertise in RTL design, C/C++ modeling, FPGA implementation, and emulation technologies. The role requires technical leadership, architecture contributions, project planning, and collaboration across design, verification, software, and platform teams.

Key Responsibilities

• Lead the design and development of synthesizable IP models for emulation and FPGA prototyping platforms.
• Contribute to architecture and micro-architecture definition, design reviews, and implementation strategies.
• Develop and optimize RTL implementations using Verilog/SystemVerilog with focus on functionality, performance, area, and timing closure.
• Develop and maintain C/C++ reference models and ensure alignment with RTL implementations.
• Drive IP integration, debug, validation, and bring-up activities across simulation, emulation, and FPGA environments.
• Support FPGA implementation activities including synthesis, timing closure, hardware validation, and performance optimization.
• Work closely with architecture, verification, software, and system teams to enable platform bring-up and software development.
• Prepare project plans, estimate schedules, identify technical risks, and drive execution to committed milestones.
• Mentor 2-4 engineers and contribute to technical guidance, code reviews, and engineering best practices.
• Drive adoption of automation, AI-assisted design methodologies, and productivity improvements.

Required Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering, or related field.
• 10+ years of experience in ASIC, SoC, FPGA, RTL design, or emulation/prototyping domains.
• Experience delivering complex IP, subsystem, or SoC projects from development through validation.

Technical Skills

• Strong expertise in synthesizable model development, Verilog/System Verilog RTL design, and ASIC/SoC design methodologies.
• Experience contributing to architecture and micro-architecture discussions and translating specifications into high-quality RTL.
• Strong C/C++ programming skills with experience developing reference models and validation frameworks.
• Good understanding of AXI/AHB/APB protocols, CDC, reset architecture, power management, and system-level integration.
• Experience with Git, CI/CD workflows, and scripting using Python, Tcl, Perl, or Shell.

Emulation & FPGA Prototyping

• Hands‑on experience with Xilinx FPGA design and prototyping flows, including AMD/Xilinx UltraScale+ and Versal architectures.
• Experience with FPGA synthesis, implementation, timing closure, debug, and hardware bring‑up using Vivado tools.
• Familiarity with Siemens Veloce/Veloce TBX, Cadence Zebu, Palladium, or equivalent emulation platforms.
• Understanding of SCE‑MI, DPI‑C, transactors, transaction‑based acceleration, software‑driven validation, and co‑emulation methodologies.

Protocol Knowledge

• Familiarity with one or more industry‑standard protocols including LPDDR5/LPDDR5X/LPDDR6, PCIe, Ethernet, USB, UART, I2C/I3C, MIPI C‑PHY/D‑PHY, AXI, AHB, and APB.

Preferred Qualifications

• Experience with large‑scale SoC prototyping, software bring‑up, and emulation‑based validation.
• Experience with multi‑FPGA partitioning and system integration.
• Familiarity with AI‑assisted semiconductor design methodologies and productivity tools.
• Exposure to HLS methodologies and cloud‑based EDA workflows.

Leadership & Soft Skills

• Strong analytical and problem‑solving skills with the ability to debug complex hardware and system‑level issues.
• Excellent communication and collaboration skills in a cross‑functional environment.
• Experience mentoring junior engineers and leading technical discussions across teams.
• Ability to plan, prioritize, and execute projects with a strong sense of ownership and accountability.
• Self‑motivated with a focus on engineering excellence, innovation, and continuous improvement.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
  OR
  Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  OR
  PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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