Staff Engineer - Standard Cell Design

Micron Technology; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Micron Technology is seeking an experienced engineer in Hyderabad to design and maintain standard cells for new DRAM products, collaborating closely with international teams on emerging technologies. The ideal candidate will have a Bachelor’s or Postgraduate degree in Electronics Engineering, with 7+ years of relevant experience in CMOS design. Skills in automation using tools such as Python and familiarity with tools like Cadence Virtuoso are essential. Join a team committed to innovation and excellence in memory technology.

Qualifications

• 7+ years of relevant experience in semiconductor technology.
• Experience in standard cell design, layout, and verification.
• Previous work experience in DRAM memory fields or analog blocks is a plus.

Responsibilities

• Design and maintain standard cells for new DRAM products.
• Collaborate with international colleagues on developing new flows.
• Develop automation test bench/flow to improve work efficiency.

Skills

CMOS circuit design

CMOS device physics and layout

Standard Cell design

Automation with Python

Interpersonal and communication skills

Education

Bachelor's or Post Graduate Degree in Electronics Engineering

Tools

Cadence Virtuoso

Primetime

Siliconsmart/Liberate

HSPICE

TCL

Python

Job description

Responsibilities

• Design and maintain standard cells for new DRAM products on new technology
• Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies
• Characterization and modeling of Standard cells to provide timing/power model
• Quality Analysis of characterized liberty models in terms of performance, Power and Functionality
• Develop automation test bench/flow/tools to improve the work efficiency and help data analysis
• Co-work with international colleagues on developing new flows and tools for stdcells design
• Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions.

Requirements

• Good understanding of CMOS circuit design
• Good knowledge of CMOS device physics and layout
• Experience in total stdcells flow from DTCO development/ spec definition till lib release
• RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow
• Finefet & planner experience required.
• Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred.
• Experience in Primetime, Solido Analytics
• Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision
• Experience in Standard Cell design, layout and verification
• Experience in Skill, TCL, Perl, Python to do test bench automation and data analysis
• Previous work experience in DRAM memory related fields or analog blocks is a plus
• Good interpersonal & communication skills and ability to work well in a team
• Experience using AI-assisted tools to improve stdcells design & char productivity, with a strong emphasis on correctness, validation, and responsible use of enterprise-approved AI systems

Education

Bachelor's or Post Graduate Degree in Electronics Engineering or related engineering field with 7+ years of relevant experience required.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.