Senior Engineer - Standard Cell Design

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 800,000 - 1,500,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad is looking for a skilled professional to design and maintain standard cells for new DRAM products, focusing on the latest technologies. Responsibilities include collaboration with the DTCO team for architecture development and identifying design pain points for AI-based automation.

The ideal candidate has strong expertise in CMOS design and experience with EDA tools like Synopsys and Cadence. Join us to innovate in the world of semiconductor technology and contribute to cutting-edge solutions.

Qualifications

• Good understanding of CMOS circuit design.
• Experiences in standard cell flow from DTCO development to RTL/GDS flow setup.
• Experience with AI-assisted tools for improving design productivity.

Responsibilities

• Design and maintain standard cells for new DRAM products.
• Collaborate with teams to develop stdcells architecture for emerging technologies.
• Identify design pain points suitable for AI automation.

Skills

CMOS circuit design

CMOS device physics

Standard cells design

Automation tools (Skill, TCL, Perl, Python)

Interpersonal and communication skills

Tools

Synopsys EDA

Cadence Virtuoso

SiliconSmart

Primetime

HSPICE

Job description

Responsibilities

• Design and maintain standard cells for new DRAM products on new technology
• Closely collaborate with the DTCO team to develop stdcells architecture for emerging technologies
• Characterize and model standard cells to provide timing/power models
• Analyze characterized liberty models in terms of performance, power, and functionality
• Develop automation test bench, flow, and tools to improve work efficiency and support data analysis
• Co‑work with international colleagues on developing new flows and tools for stdcells design
• Identify stdcells design and characterization pain points suitable for AI‑based automation and collaborate with cross‑functional teams to deploy scalable solutions

Qualifications

• Good understanding of CMOS circuit design
• Good knowledge of CMOS device physics and layout
• Experience in the total stdcells flow from DTCO development and spec definition through lib release, RTL/GDS flow setup, block‑level timing analysis, and ICC2
• Experience with Synopsys EDA flow (preferred)
• FineFET and planner experience required
• Experience in any characterization tools (SiliconSmart/Liberate) and Cadence Virtuoso (preferred)
• Experience with Primetime and Solido Analytics
• Familiarity with analog/digital simulation tools (e.g., HSPICE, HSIM, Verilog‑HDL, FINESIM, SimVision)
• Experience in standard cell design, layout, and verification
• Experience with Skill, TCL, Perl, and Python for test bench automation and data analysis
• Previous work experience in DRAM memory or analog blocks is a plus
• Strong interpersonal and communication skills and ability to work well in a team
• Experience using AI‑assisted tools to improve stdcells design and characterization productivity, with a strong emphasis on correctness, validation, and responsible use of enterprise‑approved AI systems

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.