Senior Engineer - Standard Cell Design

Micron Technology; Hyderabad; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Micron Technology, Inc is seeking a Semiconductor Design Engineer 3 in Hyderabad, India. The role involves designing and maintaining standard cells for new DRAM products while closely collaborating with the DTCO team to develop architectures for emerging technologies.

Candidates should have a strong understanding of CMOS circuit design, experience with standard cell design and tools like Cadence Virtuoso, and familiarity with automation using programming languages such as Python.

Qualifications

• Good understanding of CMOS circuit design.
• Experience in total stdcells flow from DTCO to lib release.
• Experience in Skill, TCL, Perl, Python for automation.

Responsibilities

• Design and maintain standard cells for new DRAM products.
• Collaborate with DTCO to develop stdcells architecture.
• Characterization and modeling of standard cells.

Skills

CMOS circuit design

CMOS device physics and layout

Block level timing analysis

AI-assisted tools

Test bench automation with Python

Tools

Siliconsmart

Cadence Virtuoso

Primetime

HSPICE

Job description

Job Profile(s)

Semiconductor Design Engineer 3

Responsibilities

• Design and maintain standard cells for new DRAM products on new technology
• Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies
• Characterization and modeling of standard cells to provide timing/power model
• Quality analysis of characterized liberty models in terms of performance, power and functionality
• Develop automation test bench/flow/tools to improve work efficiency and help data analysis
• Co‑work with international colleagues on developing new flows and tools for stdcells design
• Identify stdcells design & char pain points suitable for AI‑based automation and collaborate with cross‑functional teams to deploy scalable solutions

Requirements

• Good understanding of CMOS circuit design
• Good knowledge of CMOS device physics and layout
• Experience in total stdcells flow from DTCO development/spec definition to lib release
• RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow
• Finefet & planner experience required
• Experience in any characterization tools (Siliconsmart/Liberate) and Cadence Virtuoso preferred
• Experience in Primetime, Solido Analytics
• Familiar with analog/digital simulation tools, e.g. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision
• Experience in standard cell design, layout and verification
• Experience in Skill, TCL, Perl, Python to do test bench automation and data analysis
• Previous work experience in DRAM memory related fields or analog blocks is a plus
• Good interpersonal & communication skills and ability to work well in a team
• Experience using AI‑assisted tools to improve stdcells design & char productivity, with a strong emphasis on correctness, validation, and responsible use of enterprise‑approved AI systems

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.