Engineer-std cell layout

Micron Technology, Inc; Hyderabad; Sur place; INR 800 000 - 1 200 000; Plein temps

Résumé du poste

Dormont Manufacturing Co is looking for a talented individual to design and maintain standard cell layouts for new DRAM products. You will lead layout projects from spec definition to library release and collaborate with diverse teams to develop new methodologies and tools.

This role requires effective project management and the ability to guide junior team members, ensuring on-time delivery and quality standards are met. Join us in a dynamic environment where innovation meets excellence.

Responsabilités

• Design and maintain standard cells layout for new DRAM products on new technology.
• Lead the stdcells layout projects from initial spec definition to library release.
• Collaborate with DTCO team to develop stdcells architecture for emerging technologies.
• Perform layout verification and quality checks.
• Ensure on-time delivery of block-level layouts.
• Demonstrate leadership in planning and execution of projects.
• Guide junior team members in their layouts.
• Contribute to effective project management.
• Develop new methodologies to increase productivity.
• Work with Process team to negotiate DRC for new technology.
• Co-work with international colleagues on new flows and tools.

Description du poste

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities

• Design and maintain standard cells layout for new DRAM products on new technology
• Lead the stdcells layout projects from initial spec definition to till PPA qualified library release
• Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies
• Perform layout verification like LVS/DRC/Latchup, quality check and documentation
• Responsible for on-time delivery of block-level layouts with acceptable quality
• Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule and milestones in multiple project environment
• Guide junior team members in their execution of sub block-level layouts and review their work
• Contribute to effective project-management
• Develop new flows/methodologies to reduce the stdcells manual effort and increase productivity
• Closely work with the Process team, CMOS and CAD to negotiate DRC for new technology
• Co‑work with international colleagues on developing new flows and tools for stdcells layout & design

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.