Staff Engineer, ASIC IP STA

1840 Micron Tech. OP India LLP; Bengaluru; Presencial; INR 2.500.000 - 4.000.000; Jornada completa

Descripción de la vacante

Micron Technology, Inc. is seeking an ASIC IP STA Engineer (6-10 years) in Bengaluru, India. You will perform post-layout STA signoff and drive timing closure for DDR/ONFI/IO Expander IPs, collaborating with IP Design, SoC Synthesis, and SoC Physical Design teams.

Expertise in Liberty/ETM timing models and SDF/GLS is essential. The role requires strong analytical skills, experience with Cadence Tempus, Genus, Innovus, and TCL/Python for automation, and a track record of multiple tapeouts.

Formación

• 6-10 years of experience in Static Timing Analysis (STA) with a proven tapeout track record.
• Strong hands-on experience with CADENCE Tempus (preferred).
• In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes.
• Experience on high-speed memory interface IPs like DDR PHY, ONFI PHY, IO Expander IOE, or similar.
• Strong understanding of timing constraints development, validation, and debug including clocks and generated clocks.
• Experience in Liberty (.lib) and ETM timing model generation, validation and correlation.
• Ability to deliver early timing models (.lib/ETM) and high-quality timing collateral for SoC integration.
• Hands-on experience with SDF generation, validation, and Gate-Level Simulation (GLS).
• Understanding of setup/hold, recovery/removal checks, pulse-width verification, OCV/AOCV/POCV, SI-aware timing signoff.
• Experience with Cadence flow: Genus, Innovus, Tempus.
• Proficiency in TCL and/or Python for timing analysis and automation.
• Exposure to AI-driven EDA workflows for timing analysis and productivity.

Responsabilidades

• Member of the AMS IP Physical Design team responsible for post-layout STA signoff and timing closure for high-speed IPs.
• Collaborate with IP Design, SoC Synthesis, and SoC Physical Design teams during IP development and SoC integration.
• Deliver timing constraints and verify closure across functional blocks and interfaces.
• Develop and validate timing models (.lib/.ETM) and provide timing collateral for integration.
• Support SDF generation and GLS for verification teams.
• Drive timing closure across cross-functional teams with strong debugging and analysis.

Conocimientos

STA

Cadence Tempus

MMMC timing

DDR PHY

ONFI PHY

IO Expander

timing constraints

Liberty/ETM

SDF generation

GLS

Genus

Innovus

Tempus

TCL/Python

AI/ML EDA

Educación

BE/B.Tech/M.Tech

Herramientas

Cadence Tempus

Genus

Innovus

Descripción del empleo

ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI)

Member of the AMS IP Physical Design team, responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration.

6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4+ successful tapeouts.

Strong hands-on expertise with Cadence Tempus (preferred).

In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes.

Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE), or similar high-performance interface designs.

Strong understanding of timing constraints development, validation, and debug, including clocks, generated clocks, timing exceptions, and mode-specific constraints.

Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment.

Ability to deliver early timing models (.lib/ETM) and ensure high-quality timing collateral to enable smooth and predictable SoC integration.

Hands-on experience with SDF generation, validation, and Gate-Level Simulation (GLS) support for verification teams.

Solid understanding of setup/hold analysis, recovery/removal checks, pulse-width verification, OCV/AOCV/POCV methodologies, and SI-aware timing signoff.

Experience with the Cadence digital implementation and signoff flow, including Genus, Innovus, and Tempus.

Proficiency in TCL and/or Python for timing analysis, methodology development, and flow automation.

Exposure to AI/ML-enabled EDA methodologies, leveraging AI-assisted workflows for timing analysis, timing closure, constraint validation, root-cause analysis, and productivity improvement.

Strong analytical, debugging, communication, and stakeholder management skills, with the ability to drive timing closure across cross-functional teams.

Preferred Qualifications: Experience with advanced-node, high-frequency designs including LPDDR/DDR, ONFI, IO Expander, or similar memory and interface IPs.

Experience with AMS/Digital-on-Top IP development flows and timing signoff challenges associated with mixed-signal integrations.

Familiarity with AI-powered EDA solutions, Agentic AI workflows for design automation and productivity enhancement.

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all.

With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands.

Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail].

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

To learn more, please visit micron.com/careers.