Staff Engineer, ASIC IP STA

Micron Technology, Inc.; Bengaluru; Vor Ort; INR 2.500.000 - 4.500.000; Vollzeit

Benefits dieser Stelle

Medical Insurance

Paid Time Off

Zusammenfassung

Micron Technology, Inc. in Bengaluru, India, seeks an experienced Staff Engineer for ASIC IP STA to drive post-layout timing signoff and timing closure on high‑speed memory interface IPs within AMS IP Physical Design.

The role requires 6–10 years of STA experience, strong Cadence Tempus skills, and expertise in timing models (.lib/.ETM), SDF, GLS, and timing constraints. You will collaborate across IP Design, SoC Synthesis, and SoC Physical Design to enable smooth SoC integration.

Qualifikationen

• 6–10 years of STA experience with a track record of 4+ tapeouts.
• Hands-on Cadence Tempus expertise.
• Experience with high-speed Memory Interface IPs like DDR PHY/ONFI IO Expander.

Aufgaben

• Post-layout STA signoff and timing closure for high-speed IPs.
• Develop timing constraints, clocks and generated clocks; validate timing.
• Collaborate with IP Design, SoC Synthesis and SoC Physical Design teams for seamless integration.

Kenntnisse

Static Timing Analysis

Timing Closure

Debugging

Ausbildung

BE/BTech/MTech in EEE/ECE

Tools

Cadence Tempus

Lib/ETM Timing Models

Jobbeschreibung

JR111352 Staff Engineer, ASIC IP STA

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander

Location: Bengaluru, India Experience: 6-10 Years

Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI)

Key Requirements

• Member of the AMS IP Physical Design team, responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration.
• 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4+ successful tapeouts.
• Strong hands‑on expertise with Cadence Tempus (preferred).
• In‑depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes.
• Experience working on high‑speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE), or similar high‑performance interface designs.
• Strong understanding of timing constraints development, validation, and debug, including clocks, generated clocks, timing exceptions, and mode‑specific constraints.
• Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment.
• Ability to deliver early timing models (.lib/ETM) and ensure high‑quality timing collateral to enable smooth and predictable SoC integration.
• Hands‑on experience with SDF generation, validation, and Gate‑Level Simulation (GLS) support for verification teams.
• Solid understanding of setup/hold analysis, recovery/removal checks, pulse‑width verification, OCV/AOCV/POCV methodologies, and SI‑aware timing signoff.
• Experience with the Cadence digital implementation and signoff flow, including Genus, Innovus, and Tempus.
• Proficiency in TCL and/or Python for timing analysis, methodology development, and flow automation.
• Exposure to AI/ML‑enabled EDA methodologies, leveraging AI‑assisted workflows for timing analysis, timing closure, constraint validation, root‑cause analysis, and productivity improvement.
• Strong analytical, debugging, communication, and stakeholder management skills, with the ability to drive timing closure across cross‑functional teams.

Preferred Qualifications

• Experience with advanced‑node, high‑frequency designs including LPDDR/DDR, ONFI, IO Expander, or similar memory and interface IPs.
• Exposure to AMS/Digital‑on‑Top IP development flows and timing signoff challenges associated with mixed‑signal integrations.
• Familiarity with AI‑powered EDA solutions, Agentic AI workflows for design automation and productivity enhancement.

Job Profile(s):

ASIC Engineer 4

Relocation level: (TBD)

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.