Senior ASIC IP Static Timing Analysis Engineer

Micron Technology Operations India Llp; Bengaluru; On-site; INR 2,000,000 - 3,400,000; Full time

Job summary

Micron Technology is seeking an experienced Staff Engineer, ASIC IP STA based in Bengaluru to lead post-layout timing analysis and closure for high-speed IPs. You will collaborate across IP Design, SoC Synthesis, and SoC Physical Design to drive timing excellence.

The role demands 6-10 years in STA, with strong Cadence tool experience and a track record of successful tapeouts, including DDR PHY/ONFI PHY and IO Expander interfaces. AI/ML-enabled EDA familiarity is a plus.

Qualifications

• 6-10 years of experience in Static Timing Analysis (STA).
• Proven track record of 4+ tapeouts.
• Experience with high-speed memory interfaces (DDR PHY/ONFI PHY/IO Expander).
• Strong understanding of timing constraints development and debugging.
• Experience with Liberty .lib and ETM timing models.

Responsibilities

• Post-layout STA signoff and timing closure for high-speed interface IPs.
• Collaborate with IP Design, SoC Synthesis, and SoC Physical Design teams.
• Deliver timing models and timing collateral for SoC integration.
• Support SDF generation and GLS for verification teams.
• Contribute to AI/ML-enabled EDA workflows for timing analysis.

Skills

STA

Cadence Tempus

MMM timing analysis

Latch timing closure

SDF generation

Genus

Innovus

Python/TCL

Education

BE/B-Tech/M-Tech (EEE, ECE)

Tools

Cadence Tempus

Cadence Genus

Cadence Innovus

Job description

Staff Engineer, ASIC IP STA Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander

Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration.

Key Requirements

6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 + successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment . Ability to deliver early timing models (.lib/ETM) and ensure high-quality timing collateral to enable smooth and predictable SoC integration. Hands-on experience with SDF generation, validation, and Gate-Level Simulation (GLS) support for verification teams. Solid understanding of setup/hold analysis, recovery/removal checks, pulse-width verification, OCV/AOCV/POCV methodologies, and SI-aware timing signoff . Experience with the Cadence digital implementation and signoff flow, including Genus, Innovus, and Tempus . Proficiency in TCL and/or Python for timing analysis, methodology development, and flow automation. Exposure to AI/ML-enabled EDA methodologies , leveraging AI-assisted workflows for timing analysis, timing closure, constraint validation, root-cause analysis, and productivity improvement. Strong analytical, debugging, communication, and stakeholder management skills, with the ability to drive timing closure across cross-functional teams.

Preferred Qualifications

Experience with advanced-node, high-frequency designs including LPDDR/DDR, ONFI, IO Expander, or similar memory and interface IPs . Exposure to AMS/Digital-on-Top IP development flows and timing signoff challenges associated with mixed-signal integrations. Familiarity with AI-powered EDA solutions, Agentic AI workflows for design automation and productivity enhancement.

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail] Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

Experience Level Senior Level