Staff DFT Engineer

Mulya Technologies; Hyderabad; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

Mulya Technologies is seeking an experienced Staff DFT Engineer to join our semiconductor team. The role focuses on Siemens Tessent-based DFT implementation and verification across RTL, MBIST, and ATPG patterns, ensuring robust scan chains and testability for complex ASIC/SoC designs.

You will collaborate with Design, Verification, and Physical Design teams to drive DFT constraints, timing closure, and DFT automation, while delivering high-quality manufacturing patterns and debug support.

Qualifications

• 7–12 years of hands-on DFT experience in ASIC/SoC designs.
• Proficient in Siemens Tessent for DFT implementation and verification.
• Experience with DFT RTL generation, SSN/SIB/TAP, JTAG, MBIST, Boundary Scan.
• Experience in MBIST RTL/Timing Simulation and DFT timing simulation.
• Familiar with RTL, netlist, SDF, synthesis, STA, and Physical Design flows.
• Proficient in Tcl, Perl, and/or Python.
• Strong debugging, problem-solving, and communication skills.

Responsibilities

• Hands-on DFT RTL generation and integration using Siemens Tessent.
• Work with SSN, SIB, TAP/JTAG, MBIST and Boundary Scan.
• MBIST RTL timing simulation and debugging.
• Scan Stitching, Scan Compression, DFT DRC, ATPG pattern generation using Tessent.
• Create and validate manufacturing ATPG patterns for SAF and TDF.
• Validate DFT structures/patterns at RTL and gate-level/netlist, with/without SDF.
• Develop DFT constraints and support synthesis, STA, timing closure with PD.
• Timing simulations and debugging DFT timing or pattern failures.
• Collaborate across Design/Verification/Physical Design/Product/Test Eng teams.
• Support debug/resolution of DFT issues.

Skills

DFT expertise

Siemens Tessent

RTL timing sim

MBIST/Boundary Scan

Tcl/Python/Perl

Communication skills

Education

Bachelor/Master in Electrical/Electronic Engineering

Tools

Siemens Tessent

Job description

Top20 Semiconductor Organization in the world

We are a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. combine analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $10 billion in FY25, we ensure today's innovators stay Ahead of What's Possible.

We are looking for an experienced and hands-on Staff DFT Engineer with strong expertise in Siemens Tessent-based DFT implementation and verification. The role requires solid experience across DFT RTL generation, MBIST, Scan/ATPG, Boundary Scan, timing simulations, and DFT constraints.

Key Responsibilities / Experience

• Hands-on experience in DFT RTL generation and integration using Siemens Tessent.
• Strong working experience with SSN, SIB, TAP/JTAG, MBIST, and Boundary Scan, including DFT RTL generation and verification.
• Hands-on expertise in MBIST RTL simulation and timing simulation, including debugging and validation.
• Experience in Scan Stitching, Scan Compression, DFT DRC, and ATPG pattern generation using Tessent.
• Generate and validate high-quality manufacturing ATPG patterns for Stuck-at (SAF) and Transition Fault (TDF) models.
• Perform validation of DFT structures and patterns at RTL and gate-level/netlist, including simulations with and without SDF.
• Develop and validate DFT constraints and work closely with the Physical Design team for synthesis, STA, timing closure, and DFT implementation support.
• Hands-on experience with timing simulations and debugging DFT-related timing or pattern failures.
• Collaborate with Design, Architecture, Verification, Physical Design, and Product/Test Engineering teams throughout the DFT implementation cycle.
• Support debug and resolution of DFT implementation, simulation, coverage, and test-related issues.

Required Skills

• Bachelor’s/master’s degree in electrical/Electronic Engineering or a related field.
• 7–12 years of hands-on DFT experience in ASIC/SoC designs.
• Strong hands-on expertise with Siemens Tessent.
• Experience with DFT RTL Generation, SSN/SIB/TAP, JTAG, MBIST, Boundary Scan, Scan Stitching, ATPG, DFT DRC, and DFT STA constraints.
• Strong experience in MBIST RTL/Timing Simulation and DFT timing simulation.
• Good understanding of RTL, netlist, SDF, synthesis, STA, and Physical Design flows.
• Scripting experience in Tcl, Perl, and/or Python.
• Strong debugging, problem-solving, and communication skills.

Why You'll Love Working Here

At you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.

Your expertise will shape the future of technology, and you’ll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.