Senior DFT Engineer

Mulya Technologies; Hyderabad; On-site; INR 1,400,000 - 2,200,000; Full time

Job summary

Mulya Technologies in Hyderabad, India, is seeking a hands-on DFT Engineer to drive RTL generation and verification using Siemens Tessent. You will implement MBIST, Boundary Scan, and ATPG strategies across ASIC/SoC designs, ensuring robust DFT throughout the flow.

The role requires 4–7 years of DFT experience, strong debugging skills, and proficiency with Tcl/Perl/Python scripting. Collaborative work across Design, Verification, and Physical Design teams is essential.

Qualifications

• Bachelor’s/Master’s degree in electrical/electronic engineering or a related field.
• 4-7 years of hands-on DFT experience in ASIC/SoC designs.
• Strong hands-on expertise with Siemens Tessent.
• Experience with DFT RTL Generation, SSN/SIB/TAP, JTAG, MBIST, Boundary Scan, Scan Stitching, ATPG, DFT DRC, and DFT STA constraints
• Strong experience in MBIST RTL/Timing Simulation and DFT timing simulation
• Good understanding of RTL, netlist, SDF, synthesis, STA, and Physical Design flows.
• Scripting experience in Tcl, Perl, and/or Python
• Strong debugging, problem-solving, and communication skills.

Responsibilities

• Hands-on experience in DFT RTL generation and integration using Siemens Tessent.
• Work with SSN, SIB, TAP/JTAG, MBIST, and Boundary Scan, including DFT RTL generation and verification.
• MBIST RTL simulation and timing simulation, including debugging and validation.
• Scan Stitching, Scan Compression, DFT DRC, and ATPG pattern generation using Tessent.
• Generate and validate manufacturing ATPG patterns for Stuck-at and Transition Fault models.
• Validate DFT structures and patterns at RTL and gate-level/netlist, with/without SDF.
• Develop and validate DFT constraints and coordinate with Physical Design for synthesis and timing closure.
• Hands-on timing simulations and debugging DFT timing/pattern failures.
• Collaborate with Design, Architecture, Verification, Physical Design, and Product/Test Engineering during the DFT cycle.
• Support debug and resolution of DFT implementation, simulation, coverage, and test issues.

Skills

DFT experience

Siemens Tessent

RTL/Timing Simulation

Scripting Tcl/Perl/Python

Debugging & problem-solving

Education

Bachelors/Masters in Electrical/Electronic Engineering

Tools

Siemens Tessent

Job description

Top20 Semiconductor Organization in the world

We are a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. combine analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $10 billion in FY25, we ensure today's innovators stay Ahead of What's Possible.

We are looking for an experienced and hands-on DFT Engineer with strong expertise in Siemens Tessent-based DFT implementation and verification. The role requires solid experience across DFT RTL generation, MBIST, Scan/ATPG, Boundary Scan, timing simulations, and DFT constraints.

Key Responsibilities / Experience

• Hands-on experience in DFT RTL generation and integration using Siemens Tessent.
• Strong working experience with SSN, SIB, TAP/JTAG, MBIST, and Boundary Scan, including DFT RTL generation and verification.
• Hands-on expertise in MBIST RTL simulation and timing simulation, including debugging and validation.
• Experience in Scan Stitching, Scan Compression, DFT DRC, and ATPG pattern generation using Tessent.
• Generate and validate high-quality manufacturing ATPG patterns for Stuck-at (SAF) and Transition Fault (TDF) models.
• Perform validation of DFT structures and patterns at RTL and gate-level/netlist, including simulations with and without SDF.
• Develop and validate DFT constraints and work closely with the Physical Design team for synthesis, STA, timing closure, and DFT implementation support.
• Hands-on experience with timing simulations and debugging DFT-related timing or pattern failures.
• Collaborate with Design, Architecture, Verification, Physical Design, and Product/Test Engineering teams throughout the DFT implementation cycle.
• Support debug and resolution of DFT implementation, simulation, coverage, and test-related issues.

Required Skills

• Bachelor’s/master’s degree in electrical/Electronic Engineering or a related field.
• 4-7 years of hands-on DFT experience in ASIC/SoC designs.
• Strong hands-on expertise with Siemens Tessent.
• Experience with DFT RTL Generation, SSN/SIB/TAP, JTAG, MBIST, Boundary Scan, Scan Stitching, ATPG, DFT DRC, and DFT STA constraints.
• Strong experience in MBIST RTL/Timing Simulation and DFT timing simulation.
• Good understanding of RTL, netlist, SDF, synthesis, STA, and Physical Design flows.
• Scripting experience in Tcl, Perl, and/or Python.
• Strong debugging, problem-solving, and communication skills.

Why You'll Love Working Here

At you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.

Your expertise will shape the future of technology, and you’ll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.