Design for Test Engineers

Bibha.ai; Bengaluru; On-site; INR 6,75,000 - 9,00,000; Full time

Job summary

A leading semiconductor technology company is looking for skilled Design for Test (DFT) Engineers with 4-10 years of experience. The role involves developing and implementing DFT methodologies for complex SoCs and ASICs. Candidates should have strong knowledge of DFT tools and methodologies, along with excellent debugging skills. This position offers competitive compensation, health benefits, retirement plans, and ongoing training opportunities.

Benefits

Competitive salary and performance-based bonuses

Health, dental, and vision insurance

Retirement plan with employer matching

Paid time off and holiday leave

Ongoing training and professional development opportunities

Qualifications

• 4–10 years of experience in developing and implementing DFT methodologies.
• Experience in handling complex SoC/ASIC designs with multi-million gates.
• Exposure to low-power DFT techniques and advanced nodes (7nm/5nm/3nm).

Responsibilities

• Develop and implement DFT architectures for SoC/ASIC designs.
• Collaborate with teams to integrate and validate DFT features.
• Deliver high-quality test coverage while optimizing area, power, and performance.

Skills

DFT methodologies (Scan, ATPG, BIST)

Hands-on experience with DFT EDA tools

Good understanding of RTL design

Solid debugging and problem-solving skills

Excellent communication and teamwork skills

teamwork

Education

Bachelor’s/Master’s degree in Electronics/Electrical/Computer Engineering

Tools

Synopsys DFTMAX/TetraMAX

Cadence Modus

Mentor Tessent

Job description

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide end-to-end solutions in VLSI Design, Test & Product Engineering, and Embedded Systems. We work with leading semiconductor companies worldwide, enabling innovation through deep domain knowledge and engineering excellence.

Summary of the Role

We are looking for skilled and motivated Design for Test (DFT) Engineers with 4–10 years of experience in developing and implementing advanced DFT methodologies for complex SoCs and ASICs.

Key Responsibilities

• Develop and implement DFT architectures for SoC/ASIC designs.
• Utilize expertise in Scan Insertion, ATPG, MBIST, LBIST, JTAG, and Boundary Scan.
• Work on tool flows for Synopsys/Mentor/Cadence DFT tools.
• Collaborate with RTL, physical design, verification, and test teams to integrate and validate DFT features.
• Debug and resolve issues during synthesis, simulation, and silicon bring-up.
• Deliver high-quality test coverage while optimizing for area, power, and performance impact.
• Support ATE patterns generation and silicon validation.

Required Qualifications

• Must-Have:
• Strong knowledge of DFT methodologies (Scan, ATPG, BIST, Boundary Scan, JTAG, compression techniques).
• Hands‑on experience with industry‑standard DFT EDA tools (Synopsys DFTMAX/TetraMAX, Cadence Modus, Mentor Tessent).
• Good understanding of RTL design, logic synthesis, timing, and verification.
• Solid debugging and problem‑solving skills across pre‑silicon and post‑silicon phases.
• Experience in handling complex SoC/ASIC designs with multi‑million gates.
• Excellent communication and teamwork skills.
• Nice‑to‑Have:
• Bachelor’s/Master’s degree in Electronics/Electrical/Computer Engineering or related field.
• Exposure to low‑power DFT techniques and advanced nodes (7nm/5nm/3nm).
• Experience in ATE test bring‑up and production test support.

Compensation and Benefits

• Competitive salary and performance‑based bonuses.
• Health, dental, and vision insurance.
• Retirement plan with employer matching.
• Paid time off and holiday leave.
• Ongoing training and professional development opportunities.

Additional Information

• This position is part of the engineering department, and the successful candidate will report to the DFT Engineering Manager.