DFT Engineer

NXP Semiconductors NV; Hyderabad; On-site; INR 3,000,000 - 5,400,000; Full time

Job summary

NXP Semiconductors NV in Hyderabad, India seeks a hardware-focused DFT Architect to design, implement and verify DFT architectures for complex SoCs. You will collaborate with RTL, physical design and verification teams to ensure robust testability and high-quality silicon.

The role emphasizes scan, MBIST, LBIST, boundary scan, ATPG patterns, memory BIST, and ATE bring-up, with hands-on Tessent tool experience and strong problem-solving skills.

Qualifications

• Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG.
• Hands-on experience with industry standard ATPG tools.
• Proficiency in UPF/CPF-based low-power DFT.
• Knowledge of fault models (stuck-at, transition, path delay).
• Familiarity with physical design constraints for DFT.
• Experience in silicon debug and ATE bring-up.
• Hands-on experience with Tessent tools.

Responsibilities

• Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan).
• Develop and integrate scan insertion, test compression, and ATPG patterns.
• Implement memory BIST and logic BIST strategies.
• Collaborate with RTL and physical design teams for DFT insertion and timing closure.
• Perform DFT verification at RTL and gate-level simulations.
• Work with ATE teams for test program development and silicon bring-up.
• Optimize test coverage, pattern count, and test time.

Skills

DFT methodologies

Scan

MBIST

LBIST

JTAG

ATPG tools

UPF/CPF

silicon debugging

ATE bring-up

Education

Bachelor’s or Master’s in Electrical/Electronics Engineering

Tools

Tessent

Job description

You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs. You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.

Key Responsibilities

• -Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan).
• -Develop and integrate scan insertion, test compression, and ATPG patterns.
• -Implement memory BIST and logic BIST strategies.
• -Collaborate with RTL and physical design teams for DFT insertion and timing closure.
• -Perform DFT verification at RTL and gate-level simulations.
• -Work with ATE teams for test program development and silicon bring-up.
• -Optimize test coverage, pattern count, and test time.

Required Skills

• -Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG.
• -Hands-on experience with industry standard ATPG tools.
• -Proficiency in UPF/CPF-based low‑power DFT.
• -Knowledge of fault models (stuck‑at, transition, path delay).
• -Familiarity with physical design constraints for DFT.
• -Experience in silicon debug and ATE bring‑up.

Hands‑on experience with Tessent tools.

Preferred Qualifications

• - Pas experience with SoC level DFT
• -Exposure to high‑speed interfaces and DFT for mixed‑signal blocks.
• -Strong problem‑solving and communication skills.

Education

• -Bachelor’s or Master’s in Electrical/Electronics Engineering.