STA Engineer

SEMIFIVE; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

SEMIFIVE, based in Bengaluru, seeks a timing and synthesis specialist to own SoC timing closure and drive multi-mode signoff. You will coordinate with RTL, DFT, PD, and foundry teams to ensure high-quality tapeouts for global customers.

You will guide constraint development, QoR optimization, and ECO methodologies while mentoring STA engineers and shaping scalable timing flows across projects.

This role emphasizes technical leadership and end-to-end timing expertise in advanced nodes.

Qualifications

• Bachelor or master degree in electrical/Electronics/VLSI engineering with 2–5 years of STA and timing closure experience.
• Proven track record of owning top-level timing closure on multiple SoC tapeouts.
• Strong expertise in static timing analysis and synthesis flows.
• Experience with MMMC timing and constraint development.
• Deep understanding of clocking architectures and low-power interactions.

Responsibilities

• Contribute to SoC-level timing closure for complex multi-million gate designs.
• Perform top-level STA and synthesis across projects and support timing budgets.
• Own constraint development and validation at block and SoC level.
• Lead timing convergence across pre-CTS, post-CTS, and post-route stages.
• Collaborate with RTL, DFT, PD, package and foundry teams for end-to-end timing closure.
• Interface with foundry and EDA vendors on timing rules and best practices.
• Develop scalable STA and synthesis methodologies and mentor engineers.

Skills

STA

Synthesis

Timing closure

MMMC analysis

Constraint development

Clocking architectures

Low-power design

ECO flows

Debugging

Technical leadership

Education

B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering

Tools

PrimeTime

Design Compiler

Fusion Compiler

Job description

Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions. SEMIFIVE’s core business is its innovative SoC Platform that enables low-cost and high-efficiency SoC design, and also provides full turnkey silicon design services for global customers.

As the cost of developing an SoC and the demand for customized silicon continue to grow rapidly, SEMIFIVE’s SoC Platform plays a critical role in turning innovative ideas into silicon. SEMIFIVE works closely with global technology leaders and is rapidly emerging as The New Global Hub of Custom Silicon.

Semifive India Design Centre, headquartered in Bangalore, is a rapidly growing capability centre responsible for delivering complex, multi-node SoC programs for global customers across the US, Europe, and Asia. The India team owns front-end through back-end execution, including RTL, STA, synthesis, physical design, and signoff for turnkey silicon programs.

Key Responsibilities

SoC Timing & Synthesis Execution

• Contribute to SoC-level timing closure for complex, multi-million gate designs.
• Perform top-level and block-level STA and synthesis activities across projects.
• Support timing budgeting, constraints development, and closure strategies.
• Participate in timing signoff activities and ensure quality delivery.

Execution & Technical Ownership

• Drive multi-mode multi-corner (MMMC) timing signoff, including functional, scan, and low-power modes.
• Own constraint development and validation (SDC) at block and SoC level.
• Lead timing convergence across pre-CTS, post-CTS, and post-route stages.
• Partner closely with physical design, clocking, power, and DFT teams to resolve complex timing challenges.
• Guide synthesis strategy including hierarchical vs flat synthesis, QoR optimization, and ECO methodologies.

Cross-Functional & Foundry Collaboration

• Work closely with RTL, DFT, PD, package, and foundry teams to ensure end-to-end timing closure.
• Interface with foundry and EDA vendors on advanced node timing issues, signoff rules, and best practices.
• Support customer design reviews, timing signoff discussions, and technical escalations.
• Define and standardize STA and synthesis methodologies across Semifive programs.
• Develop automation, checks, and best practices for scalable and predictable timing closure.
• Mentor and guide STA and synthesis engineers, building strong technical depth within the team.
• Review and approve timing signoff checklists, reports, and tapeout readiness.

Qualifications

• B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering.
• 2-5 years of experience in STA, synthesis, and timing closure for complex SoCs.
• Proven track record of owning top-level timing closure on multiple successful SoC tapeouts.
• Strong expertise in: Static Timing Analysis (PrimeTime or equivalent)
• Synthesis flows (Design Compiler, Fusion Compiler)
• MMMC analysis and advanced constraint development
• Deep understanding of: Clocking architectures (multiple clocks, generated clocks, CDC implications)
• Low-power design and timing interactions (UPF/CPF)
• Scan and test-mode timing closure
• ECO flows and late-stage timing fixes
• Experience working on advanced technology nodes (12nm and below).
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication skills with ability to lead cross-functional and global teams.

Why Join Us?

At Semifive, you will play a critical technical leadership role in delivering first-time-right silicon for global customers. Unlike traditional large semiconductor organizations, Semifive offers broad ownership and real impact, where timing and synthesis leaders directly influence architecture, implementation strategy, and final silicon quality.

As part of Semifive India, you will work on multiple complex SoCs, partner with world-class engineering teams across geographies, and help build scalable STA and synthesis methodologies for a rapidly growing organization.

This role offers the opportunity to shape not just individual chips — but how silicon is built at Semifive.