Senior Staff Engineer, Static Timing Analysis (STA) Lead

SiFive, Inc.; Bengaluru; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

A leading technology company in Bengaluru is seeking a Senior Staff Engineer for Static Timing Analysis (STA) to lead timing signoff for high-speed data center CPUs. The ideal candidate will have 10+ years of experience, a strong background in timing methodologies, and expertise with Synopsys PrimeTime. Responsibilities include driving innovation, managing SDC quality, and collaborating with cross-functional teams. This position also offers opportunities in advanced nodes, particularly 3nm and exposure to 2nm technology.

Qualifications

• 10+ years of experience in timing-related roles at high-performance CPU designs.
• Expertise in Synopsys tools and deep understanding of timing signoff processes.
• Experience with Sourcing through Place and Route (P&R) transitions.

Responsibilities

• Lead all timing-related aspects of next-generation, high-speed CPUs.
• Drive advanced timing methodologies and innovation for design closure.
• Manage the development of constraint management and quality assurance.

Skills

Timing Signoff & Tools

Advanced Node Experience

Physical Design Flow

SDC Proficiency

Advanced Clocking

Education

Bachelor's or Master's in E&E, ECE, CS, VLSI, or PhD

Tools

Synopsys PrimeTime

Synopsys FusionCompiler

Job description

Senior Staff Engineer, Static Timing Analysis (STA) Lead page is loaded## Senior Staff Engineer, Static Timing Analysis (STA) Leadlocations: Bengaluru, Karnataka, Indiatime type: Full timeposted on: Posted Todayjob requisition id: R-101129## ****About SiFive*****As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.*At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our and pages.**Job Description:****About the Role** We are seeking a highly experienced STA Engineer to serve as the primary technical authority and owner for all timing-related aspects of our next-generation, high-speed data center scale CPUs. In this role, you will define sign-off criteria, drive advanced timing methodologies, and spearhead innovation to accelerate timing closure for massive, high-performance compute architectures at cutting-edge process nodes (N3/N2).**Key Responsibilities*** **Technical Leadership:** Act as the primary point of contact and subject matter expert for all STA and timing-related items across the high-speed CPU design team.* **Methodology Innovation:** Develop and deploy "correct-by-construction" methodologies to proactively drive timing convergence early in the design cycle.* **Platform Development:** Architect and maintain advanced tracking platforms to monitor and analyze timing convergence metrics across complex data center CPU blocks.* **Constraint Management:** Lead SDC quality assurance. Collaborate closely with cross-functional partners to ensure pristine, high-quality SDCs through our internal flows**Required Qualifications*** **Timing Signoff & Tools:** Deep, authoritative understanding of the complete Timing Signoff process (defining criteria, margins, and closure). **Expertise in Synopsys PrimeTime is a must.*** **Advanced Node Experience:** Proven, hands-on experience taping out complex designs at the 3nm (N3) process node.* **Physical Design Flow:** Strong working knowledge of the physical design flow, specifically transitioning from Synthesis through Place and Route (P&R).* **SDC Proficiency:** Extensive experience in developing, managing, and debugging complex SDCs for massive SoC or CPU designs.* **Advanced Clocking:** Strong understanding of Clock Tree Synthesis (CTS) architectures, including Mesh and Multi-Source CTS (MSCTS).* **Education Qualification:** A bachelor's or master's in E&E, ECE, CS, VLSI, or PhD is required with 10+ years of experience.**Preferred Qualifications*** **High-Performance Compute:** Direct, proven experience driving timing closure specifically for high-speed, data center scale CPUs.* **Next-Gen Nodes:** Exposure to or active experience with 2nm (N2) technology nodes is highly preferred.* **Advanced EDA Tools:** Hands-on experience with Synopsys FusionCompiler is highly preferred.* **AI/ML Integration:** Knowledge of Machine Learning (ML)-based timing prediction techniques to reduce design iterations and accelerate sign-off cycles.**Additional Information:**This position requires a successful background and reference checks and satisfactory proof of your right to work in:IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.