STA Engineer

Weekday AI; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Weekday AI in Bengaluru is seeking an experienced STA Engineer to lead timing closure for complex ASIC/SoC designs. You will develop and validate timing constraints, perform MMMC-based STA, and collaborate with RTL, DFT, physical design, and verification teams to meet tight timing goals.

The role requires hands-on expertise with Cadence Tempus and Synopsys PrimeTime, SDF generation, and IP-level timing models, plus strong written and verbal communication across multi-disciplinary teams.

Qualifications

• 6–12 years of experience in ASIC/SoC timing signoff.
• Hands-on STA engineer with strong timing closure expertise.
• Deep knowledge of STA and timing constraints.
• Experience with MMMC timing analysis in both functional and DFT modes.
• Experience with Cadence Tempus and/or Synopsys PrimeTime, preferably both.
• Strong writing and debugging of SDC constraints.

Responsibilities

• Collaborate with RTL, DFT, and physical design teams to drive timing closure.
• Develop and validate block-level and top-level timing constraints.
• Perform STA and timing analysis across corners and modes.
• Execute MMMC-based STA and timing closure for functional and DFT modes.
• Analyze timing violations and work with teams to resolve them.
• Perform synthesis analysis and assess impact on timing, area, and power.
• Work with DFT teams to address scan/test timing requirements.
• Generate and validate SDF files and support GLS.
• Create ETM/timing models at IP level.
• Support signoff activities and improve STA methodologies and automation.
• Document timing analysis results and signoff requirements.

Skills

STA experience

Timing closure

Synthesis & DFT

Cadence Tempus

Synopsys PrimeTime

SDC constraints

SDF generation

ETM timing models

IP integration

Tools

Cadence Tempus

Synopsys PrimeTime

Job description

This role is for one of Weekday’s clients

Min Experience: 6+ years
Location: Bengaluru
JobType: full-time

We are looking for an experienced STA Engineer with 6–12 years of hands‑on experience in Static Timing Analysis, synthesis, DFT, and timing closure for complex ASIC/SoC designs. The ideal candidate will have strong expertise in developing and validating timing constraints, performing MMMC‑based STA, and supporting designs through implementation, signoff, and gate‑level verification.

You will work closely with design, SoC, DFT, physical design, and verification teams to understand design requirements, establish timing methodologies, identify timing issues, and drive successful timing closure across functional and DFT modes.

Requirements

Key Responsibilities

• Work closely with RTL and design teams to understand design requirements, clocking architecture, timing objectives, and design constraints.
• Develop, write, and implement block-level and top-level timing constraints for synthesis and Static Timing Analysis.
• Perform comprehensive STA and timing analysis across different operating modes and process‑voltage-temperature corners.
• Execute MMMC‑based STA and timing closure for both functional and DFT modes.
• Analyze setup, hold, recovery, removal, clock skew, uncertainty, and other timing violations, and work with relevant teams to resolve them.
• Perform synthesis analysis and understand the impact of synthesis decisions and constraints on timing, area, and power.
• Work with DFT teams to analyze timing requirements associated with scan and test modes and ensure timing closure across DFT scenarios.
• Perform STA using industry‑standard tools, preferably with hands‑on experience in both Cadence Tempus and Synopsys PrimeTime.
• Generate and validate SDF (Standard Delay Format) files and support functional verification teams during Gate‑Level Simulation (GLS).
• Generate and validate ETM/timing models at the IP level for accurate timing abstraction and integration.
• Collaborate with SoC teams to support IP integration and timing closure at the SoC level.
• Perform Lint and CDC analysis, identify design issues, and collaborate with RTL/design teams on resolution.
• Debug timing and constraint‑related issues and provide actionable recommendations to design and implementation teams.
• Support signoff activities and contribute to improving STA methodologies, scripts, flows, and automation.
• Document timing analysis results, methodologies, constraints, and signoff requirements.

Must‑Have Skills

• 6–12 years of experience in ASIC/SoC design methodology, STA, or timing signoff.
• Strong hands‑on experience as an STA Engineer.
• Excellent understanding of Static Timing Analysis (STA) and timing closure.
• Strong working knowledge of Synthesis and DFT concepts and flows.
• Hands‑on experience with MMMC timing analysis in both functional and DFT modes.
• Experience with Cadence Tempus and/or Synopsys PrimeTime, preferably both.
• Strong expertise in writing and debugging SDC constraints at block and top levels.
• Experience with SDF generation and validation and support for GLS.
• Experience in ETM/timing model generation and validation at IP level.
• Working knowledge of Lint and CDC methodologies and tools.
• Strong understanding of clocks, clock domains, timing paths, exceptions, false paths, multicycle paths, and timing constraints.
• Ability to collaborate effectively with RTL, physical design, DFT, verification, and SoC teams.

Good‑to‑Have Skills

• Experience working on complex SoC, CPU, GPU, networking, or high‑performance ASIC designs.
• Knowledge of physical‑design‑related timing optimization and signoff flows.
• Scripting experience in Tcl, Python, or Shell for STA automation and flow development.
• Experience with hierarchical timing analysis and IP‑to‑SoC timing integration.
• Understanding of advanced‑node timing challenges and low‑power design methodologies.
• Strong debugging, analytical, and problem‑solving skills.