Sr. VLSI Signoff Engineer/ 5+ years/ Bangalore

ISOURCE SERVICES; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

A leading tech firm in Bengaluru is seeking a Senior VLSI Signoff Engineer with over 5 years of experience. The ideal candidate must have strong expertise in Static Timing Analysis, Physical Verification, and Power Supply Integrity for advanced SoC designs. Key responsibilities include STA signoff using PrimeTime, executing Physical Verification using Calibre, and ensuring tape-out readiness. This role requires collaboration with design, PD, and foundry teams. Competitive salary and benefits offered.

Qualifications

• 5+ years of hands-on experience in VLSI signoff.
• Expertise in STA, DRC, LVS, ERC, and Power Integrity.
• Experience with advanced technology nodes.

Responsibilities

• Perform STA signoff using PrimeTime.
• Handle OCV/AOCV/POCV analysis and ECO flows.
• Execute Physical Verification using Calibre.
• Perform PSI signoff using Voltus.
• Address signoff challenges and ensure tape-out readiness.
• Collaborate with design and foundry teams.
• Apply and validate foundry rule decks.

Skills

Static Timing Analysis (STA)

Physical Verification

Power Supply Integrity (PSI)

PrimeTime

Calibre

Voltus

Job description

Sr. VLSI Signoff Engineer/ 5+ years/ Bangalore

iSource Services is #Hiring for the position of Senior #VLSISignoffEngineer

About the Role:

We are seeking highly experienced VLSI Signoff Engineers with strong hands‑on expertise in Static Timing Analysis (STA), Physical Verification, and Power Supply Integrity (PSI) for advanced SoC designs. The ideal candidate will have deep signoff experience at advanced technology nodes and a solid understanding of foundry signoff methodologies.

Key Responsibilities:

• Perform STA signoff using PrimeTime, including setup/hold analysis and closure
• Handle OCV/AOCV/POCV analysis and drive ECO flows for timing closure
• Execute Physical Verification using Calibre (DRC, LVS, ERC)
• Perform Power Integrity / PSI signoff using Voltus: Static IR drop, Dynamic IR drop, Electromigration (EM) analysis
• Address advanced-node signoff challenges and ensure tape‑out readiness
• Work closely with design, PD, and foundry teams to resolve signoff issues
• Apply and validate foundry rule decks and follow industry‑standard signoff methodologies

Qualifications:

• 5+ years of exclusive, hands‑on industry experience in VLSI signoff
• Strong expertise in PrimeTime – STA signoff (setup/hold, OCV/AOCV/POCV, ECO)
• Strong expertise in Calibre – DRC, LVS, ERC
• Strong expertise in Voltus – Power Integrity / PSI signoff (IR, EM)
• Proven experience with advanced technology nodes
• Solid understanding of foundry rules, signoff flows, and best practices

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